Re: Fw: [SI-LIST] : via capacitance

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From: Ray Anderson ([email protected])
Date: Tue Mar 28 2000 - 00:17:53 PST

John Keeble wrote:

                ... text deleted ....
> I used to think that it was useful to minimise the inductance between the
> bypass caps and the power planes. However, each capacitor has a low
> impedance over a range of frequencies centered on its self resonance, and an
> extra nH or two simply moves this range down. Recent work revealed in this
> list shows that a number of different, close-spaced values can deliver a low
> impedance over the full spectrum.

Just one real quick comment on that last statement. While it is true that
extra mounting inductance from longer vias will cause the resonant frequency
of a decoupling capacitor to decrease a bit, there is another effect
to be considered.

Extra mounting inductance causes the Q of the resonance associated
with the interaction of multiple decoupling capacitors to increase.
This causes the high impedance anti-resonance (actually a parallel
resonance) peak observed in a frequency domain scan to increase in amplitude.
With moderate ESR capacitors this isn't too problematic, however if
you are using very low ESR parts the high impedance peaks can become
difficult to manage.

The bottom line is: if you are using low ESR decaps, make sure you take
care to minimize the mounted inductance of the parts. The mounted inductance
is composed of 3 parts: the parasitic inductance in the capacitor itself,
the inductance associated with the loop area of the mounting stucture
(pad separation, escape position, via length), and also the spreading
inductance of the plane pair which is stackup dependent. The portion
contributed by the partial inductance of the mounting structure is usually
the largest part of the total inductance.

Ray Anderson
Sun Microsystems

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