RE: [SI-LIST] : Parallel Plate Capacitance for Bypass

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From: Grasso, Charles (Chaz) ([email protected])
Date: Tue Mar 28 2000 - 15:11:55 PST

You might be interested in a project led by NCMS that is the
National Centre for Manufacturing Sciences on Embedded

Details may be found at
Goto Archives and look at the download available in October and November of
Thank you
Charles Grasso
2270 Sth 88th Street
Louisville CO 80027
Tel: (303)673-2908

> ----------
> From: Hansen, Chris[SMTP:[email protected]]
> Sent: Friday, March 24, 2000 1:25 PM
> To: SI List (E-mail)
> Subject: [SI-LIST] : Parallel Plate Capacitance for Bypass
> According to specifications, X7R type chip capacitors used for power
> subsystem bypass seem to become ineffective above 150 to 200 Mhz.  For
> frequencies higher up, you are reliant upon the internal parallel plate
> capacitance.  I have two questions. 
> 1. Is the calculation for the required capacitance that is needed for the
> parallel plate capacitance the same as that used for a discrete chip
> capacitor bypass network, or is there a conservation of charge situation
> where the real answer is Cpp*dVnoise = Cload*dVchange? (where Cpp =
> parallel plate capacitance, dVnoise = tolerable change in power supply
> voltage, Cload = sum of load capacitance being switched simultaneously,
> dVchange = voltage change through driver output switch). 
> 2. If you have a power plane sandwiched between 2 ground planes, does the
> parallel plate capacitance double for a given area?
> Thank you,
> Chris Hansen
> Sr. Design Engineer
> DPT & Adaptec Companies

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