From: Greim, Michael ([email protected])
Date: Mon Mar 27 2000 - 12:13:22 PST
right manitude wrong units. Thanks for pointing that
out. Should read.....
Cplane = 0.225*4.1/.002 = roughly 460 pF
Sorry bout that......
MG
> -----Original Message-----
> From: S. Weir [SMTP:[email protected]]
> Sent: Monday, March 27, 2000 3:01 PM
> To: [email protected]
> Subject: RE: [SI-LIST] : Parallel Plate Capacitance for Bypass
>
> Ohms???
>
> 3-4 mils is quite common in high layer count boards. 4 seems to be no
> charge, 3 has a somewhat lower yield, but not bad at the better houses.
>
> Regards,
>
>
> Steve.
> At 02:23 PM 3/27/2000 -0500, you wrote:
> >Coupla things.......
> >
> >You appear to be off by a factor of 2 somewhere. Plane
> >capacitance is defined as
> >
> > Cplane = (0.225*Er*A)/d
> >
> >for a 2 mil core, with A being 1 square inch, this becomes
> >
> > Cplane = 0.225*4.1/.002 = roughly 460 ohms
> >
> >With standard FR4 you can run into a couple of problems
> >that you might want to check on. Thin core materials can
> >prove to be quite costly and i have heard that during laminating
> >that all the resin can be squeezed out creating air pockets.
> >Therefore, before going with a standard material, you might
> >want to consider the benefit to cost tradeoffs of materials that
> >are targetted for this purpose such as Emcap or BC2000.
> >I found good information on these materials on the Hadco and
> >Merix web sites.
> >
> >I would also recommend running a frequency simulation on
> >your PDS to make sure that you don't have frequency regions
> >that have very high impedances. Suffice it to say that bad
> >things will occur in your system if this occurs. There are a
> >number of good resources (most notably and referenced,
> >those by Larry Smith et al.) available on the web to help
> >you with your design. You might also want to check out
> >Istvan Novaks website as he has a great paper and utility
> >for general download. He can be found at:
> >
> > home.att.net/~istvan.novak/
> >
> >Best of Luck,
> >
> >Michael Greim
> >
> > > -----Original Message-----
> > > From: Ron Miller [SMTP:[email protected]]
> > > Sent: Monday, March 27, 2000 1:39 PM
> > > To: [email protected]
> > > Subject: Re: [SI-LIST] : Parallel Plate Capacitance for Bypass
> > >
> > > Thanks Steve, I knew it was somewhere around there.
> > >
> > > So, by extension, 2.2 mil dielectric, available at very little if any
> > > extra cost should be about 1000pf/in sq for FR4
> > > and eliminatee the need for discrete capacitors below 1000 pf.
> > >
> > > ron
> > >
> > > "S. Weir" wrote:
> > >
> > > Ron,
> > >
> > > 5 mils should yield about 200pF / in sq, before taking away for
> > > vias.
> > >
> > > Regards,
> > >
> > >
> > > Steve.
> > > At 02:30 PM 3/24/2000 -0800, you wrote:
> > >
> > > Chris
> > >
> > > Go to the AVX webpage and the American Technical
> Ceramics
> > > web
> > > pages. They have S-parameters which show that the
> smaller
> > > profile
> > > ceramics are good to above 1 Ghz.
> > >
> > > Small profile usually means smaller capacitance so you
> may
> > > need
> > > a small one of .01 uf and a larger one of about .47 uf.
> > >
> > > For frequencys 3 Ghz and up use a capacitive layer in
> your
> > > board. Recently I heard that with 5 mil FR4 dielectric
> you
> > > get about
> > > 100pf per square inch. So, using a 2 mil layer would
> give
> > > about 7.5 X
> > > this value(per square inch).
> > >
> > > Ron Miller
> > >
> > >
> > >
> > >
> > > According to specifications, X7R type chip
> > > capacitors used for power subsystem bypass seem to become ineffective
> > > above 150 to 200 Mhz. For frequencies higher up, you are reliant upon
> the
> > > internal parallel plate capacitance. I have two questions. 1. Is the
> > > calculation for the required capacitance that is needed for the
> parallel
> > > plate capacitance the same as that used for a discrete chip capacitor
> > > bypass network, or is there a conservation of charge situation where
> the
> > > real answer is Cpp*dVnoise = Cload*dVchange? (where Cpp = parallel
> plate
> > > capacitance, dVnoise = tolerable change in power supply voltage, Cload
> =
> > > sum of load capacitance being switched simultaneously, dVchange =
> voltage
> > > change through driver output switch). 2. If you have a power plane
> > > sandwiched between 2 ground planes, does the parallel plate
> capacitance
> > > double for a given area?Thank you,Chris HansenSr. Design EngineerDPT &
> > > Adaptec Companies
> > >
> > > --
> > > Ronald B. Miller _\\|//_ Signal Integrity Engineer
> > > (408)487-8017 (' 0-0 ')
> > > fax(408)487-8017
> > > ==========0000-(_)0000===========
> > > Brocade Communications Systems, 1901 Guadalupe Parkway,
> San
> > > Jose,
> > > CA 95131
> > > [email protected], [email protected]
> > >
> > >
> > > --
> > > Ronald B. Miller _\\|//_ Signal Integrity Engineer
> > > (408)487-8017 (' 0-0 ') fax(408)487-8017
> > > ==========0000-(_)0000===========
> > > Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA
> > > 95131
> > > [email protected], [email protected]
> > >
> >
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