From: Mike Jenkins ([email protected])
Date: Wed Mar 22 2000 - 17:05:24 PST
I think others may have already covered this, but just in case...
The 1 nF blocking capacitor on a 75 line has a time constant of
150 ns. If your transmitter output does not start out balanced
(that is, both outputs at the same voltage), you'll see garbage
for several time constants. What you see on the scope for
hardware is steady state, well past this transient which can
mess up your simulation output. Transmitter stimuli we use
in simulation all start out like this...
_____________ _______ _____________...
___________/ \/ \/
Hope that helps.
> Kai Keskinen wrote:
> Hi SI Folk:
> I had a lot of problems getting a spice model of a gigabit ethernet
> chip to run properly. The differential outputs are tied to ground with
> 4.5kOhm resistors and then coupled to the long T-lines (W-element)
> with ~1nF caps. They are terminated with 100ohms across the
> differential pairs just before the receiver. It turned out that if we
> did not set the initial charging conditions on the coupling caps to a
> very narrow range of values, the simulation never actually worked. One
> or both of the differential outputs did not at all resemble what the
> chip should transmit even for very long simulation times.
> My questions are: Why did the circuit not charge up the caps and then
> work as would happen in reality? Is this a very common effect when
> running HSPICE or other sims?
> Kai Keskinen
> Equipment and Network Interconnect
> Nortel Subsystems and Performance Networks (NSPaN)
> (613)-765-3506 (ESN 395)
> [email protected]
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Mike Jenkins Phone: 408.433.7901 _____ LSI Logic Corp, ms/G715 Fax: 408.433.7461 LSI|LOGIC| (R) 1525 McCarthy Blvd. mailto:[email protected] | | Milpitas, CA 95035 http://www.lsilogic.com |_____| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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