From: Gaines, William ([email protected])
Date: Tue Mar 21 2000 - 09:01:50 PST
I do not know about Orcad, but in VeriBest2000 (now part of mentor) you can create a "layout cell" that has traces as part of the cell. On the schematic you would just show the IC, but this would point to this special cell. You would probably need to coordinate the reference designators (so C1 is the cap for U1 etc.) But this can be handled in the notes of the Assembly drawing.
If your version of Orcad doesn't allow this, perhaps a graphic, on the component layer, with the cap layout could be copied to each location. This would unfortunately cause trouble with any design rule checking tools that you use.
You may find that by the time you figure out all the bugs in doing the "end run" that you might as well have placed them anyway. Do a test route on a couple of configurations (with just one or two IC's). Place all of the IC's, Then place each set of caps in your "preferred" locations. If you have an auto-router, let it route these voltages at least. (the whole design, if the auto-router is a good one) If you do not have an auto router, (sorry I do not know much about the Orcad tool) you should be able to copy the "preferred" power routing to each IC type. Coordinating the Capacitor reference designators can help out allot. I have used schemes like C101 for the v+ cap, C201 for the v- cap, for the U1 opamp. with the C1-C100 for the other signal caps.
Hope this helps,
Bill Gaines
Sr. Engineer, Electronic Packaging, Aerojet, Azusa
626-812-2199 m-f 7-3:30 626-969-5772 fax
[email protected] 626-849-2324 pager
> ----------
> From: Yu Wang[SMTP:[email protected]]
> Reply To: [email protected]
> Sent: Tuesday, March 21, 2000 7:42 AM
> To: [email protected]
> Subject: [SI-LIST] : how to combine multi components together with Orcad layout
>
> Hi, all experts there,
> I am using Orcad(Ver.9.0) Layout plus to implement my
> design in which more than 30 pieces SMT FIFOs(TQFP128)
> and more than 70 pieces SMT 16 bit buffers and
> latchs(TVSOP48) are used. So I have to lay more than
> 250 decoupling capacitors down and connect them to the
> PWR and GND pins. It's a tough work. However, because
> the layout and the connections of the capacitors for
> each FIFO or for each TVSOP48 chip are same. Then I
> think I can combine one FIFO and its capacitors
> together and regard them as one unit. It will simplify
> the job definitely. But I haven't found the tool
> within Orcad to realize it. What I am doing is
> creating a new layout pattern in which I use obstacle
> to draw some of the footprints of the chip and all the
> footprints of the capacitors and all the connections
> just like the old Orcad layout library did. Right now,
> for prototype,
> it can work good because I can solder the capacitors
> by hand. But, what I am worrying about is that in the
> future when I send it to production, the capacitors
> would not be assembled by machine. That will be a
> nightmare.
> So please, give any suggestions. Thanks a lot.
>
>
>
> =====
> Yu Wang, Ph.D
> U.T. MD Anderson Cancer Center
> 1100 Holcombe Blvd., Box 217
> Houston, TX, 77030
> Tel:713-745-1671
>
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