From: S. Weir ([email protected])
Date: Sun Mar 19 2000 - 02:41:15 PST
Shayle,
The best that we can do is to reduce the probability that a metastable
condition will propagate. The generally accepted metastability equation is
based on observations conducted with a two stage shift register circuit.
MTBF_2stage = ( e^( -k1 )) / ( k2*Fclk*Fstim )
k1 = metastable resolution constant
k2 = metastable susceptability window
Fclk = sampling clock frequency
Fstim = Asynchronous input stimulus frequency
What may not have been clear in Dr. Johnson's article is that the time for
a metastable event to resolve at any single stage is
statistical. Metastability is akin to a marble on an upside-down salad
bowl. In a vibration free environment, it is possible to balance the
marble, and have it stay put. However, to be vibration free, we would have
to be at absolute zero.
Since, we don't encounter absolute zero very often, we have a source of
noise energy to push the marble one way or another. Sooner or later, the
push will be enough to get the marble moving. The sentence:
"The metastable resolution delay at the output of the first
flip-flop in the chain causes a problem ONLY if it hits RIGHT ON
TOP of the actual metastable sampling window for the second flip-
flop."
refers to the output of the first stage still slewing through the
metastable voltage window of the second FF, duing the metastable
susceptible window of the second FF. It is under this condition that the
second stage of the shift register fails to update properly. If you want
this in VHDL code:
entity ms_test
port
(
clk : in std_logic ;
stimulus : in std_logic ;
error : out std_logic
) ;
end ms_test ;
architecture behave of ms_test is
signal inp_q : std_logic ;
signal tst_qa : std_logic ;
signal tst_qb : std_logic ;
begin
p_ff_re : process( clk )
if( rising_edge( clk ) ) then
inp_q <= stimulus ;
tst_qa <= inp_q ;
end if ;
end p_ff_re ;
p_ff_fe : process( clk )
if( falling_edge( clk ) ) then
tst_qb <= inp_q ;
error <= '1' when( tst_qa /= tst_qb ) else '0' ;
end if ;
end p_ff_fe ;
end ;
Since the formula just characterizes the behavior of two FF's, it is
relatively straightforward to extrapolate the case for three.
Regards,
Steve.
At 03:31 PM 3/18/2000 +0000, you wrote:
>Dr. Johnson writes:
>
>"Sometimes we use a chain of synchronizing registers when sampling and
>asynchronous signal. In a chain of synchronizers, things work a little
>differently. The metastable resolution delay at the output of the first
> flip-flop in the chain causes a problem ONLY if it hits RIGHT ON
>TOP of the actual metastable sampling window for the second flip-
>flop. Since this second window is extremely narrow (much narrower
>than the worst-case published specifications for setup and hold times),
>your MTBF calculations benefit not only from the amount of resolution
>time T made available by each stage, but also from the width of the
>resolution windows. In mathematical terms, the output transition from th
> first stage has to hit between T and T+dT, where dT is the window width
>of the second stage, in order to cause an error. This effect renders a
>two-stage (or three-stage) sampler running at rate R almost as
>effective as a single-stage sampler using a slower clock of R/2 (or
>R/3)."
>
>My question is regarding how to determine the clock frequency with two or
>more successive flip-flops.
>
>By just using one, the clock period is the traditional tCO + tSU +
>tPATH_DELAY + tMETA_RESOLUTION_TIME, where the tMETA_RESOLUTION_TIME is
>selected from a statistical table based upon the acceptable mean time
>between failures.
>
>Now, with two or more synchronizing FF's, as you state, the clock frequency
>is greatly reduced. I assume it cannot be reduced all the way to the point
>of no additional time for metastate resolution.
>
>As usual, given the minimum required mean time between failures traded off
>against the minimum design frequency, how is this increased frequency now
>calculated using two or more FF's?
>
>Thank you in advance.
>
>Shayle
>
>
>
>
>*************************************************************
>Shayle I. Hirschman, Senior Engineer
>Managing Director
>Digital Design Solutions
>http://www.digital-designs.com
>[email protected]
>Phone 901/759-1802 Fax 901/759-2324
>
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