From: Larry Smith ([email protected])
Date: Fri Mar 17 2000 - 13:05:02 PST
Boy, I would not count on high power distribution impedance to slow
down my edge rates. The edge rate would then be dependent on how many
signals decided to switch at once. Timing would be a nightmare, not to
mention SSN problems.
We work very hard to provide low impedance, rock solid power supplies
to the power pins of every chip. Let the chip determine the edge
rate. Generally, we are trying to make the edges as fast as possible
as we push to the very highest bandwidth possible. I know this is not
what the EMI guys want to hear, but we must design them both fast and
quiet. There is no market for the slow stuff. Anyway, it gives us all
jobs and something to talk about.
Vinu Arumugham wrote:
> Larry Smith wrote:
> > To directly answer Mark's questions, with the same amount of noise
> > stimulation, there will be much more noise between the 40 mil power
> > planes than between the 4 mil planes, in fact 10X. The reason is
> > because of the increased impedance.
> Doesn't increased power distribution impedance equate to slower logic transition
times? If so, the amount of noise stimulation is not the same. If the design's timing
margin allows for slower edge
> rates, would 40 mil planes not be better than 4 mil planes?
**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:44 PDT