Re: [SI-LIST] : Fast edges with limited plane capacitance

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From: Doug McKean ([email protected])
Date: Fri Mar 17 2000 - 11:02:36 PST

mjs wrote:
> Let's assume that a power subsystem has a low, flat impedance up to a few
> hundred MHz, and has a pair of realtivly unbroken planes. Only problem is
> that the stackup is s-G-s-s-P-s since the engineer has insisted that EMI
> will be a problem unless all noisy digital signals are 'sandwiched'
> between the planes. This board also has parts with 1-2ns edge rates.
> I am arguing that s-s-G-P-s-s is the preferred stackup, as this would
> allow the planes to be 4-5mils apart instead of 40mils on an .062" card,
> yielding much greater plane capacitance.
> My questions is this: How does a lack of planar capacitance contribute
> to increasing EMI? It seems that not having the proper plane capacitance
> would tend to slow edge rates and possibly be one of the lesser SI sins.
> Also: Is there any validity to the s-G-s-s-P-s 'copper sandwich'
> decreasing EMI?

I would start the discussion by saying the
question stems from mixing actually two
entirely different concepts:

1. Near field effect decoupling,
   i.e. interplanar capacitive effects


2. Far field effect shielding,
   i.e. shielding effectiveness

While the s-s-G-P-s-s stackup allows for better
decoupling between G-P, it can also lead to poor
far field performance, which is difficult to predict
to say the least, and is dependent upon not only
planar but interplanar routing of traces, etc ...
But then, there is no shielding effectiveness of
the traces to the outside world.

The s-G-s-s-P-s stackup allows one to "bury" high
speed/fast edge rate and clock signals into the
middle two planes with the shielding effectiveness
of the G and P planes. *Possibly* at the cost of
decoupling the G and P planes. - Doug McKean

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