RE: [SI-LIST] : Bad IBIS models!

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From: Muranyi, Arpad ([email protected])
Date: Fri Mar 17 2000 - 10:32:08 PST

As some have already pointed out, this problem comes from the
low quality of the SPICE model itself. Contrary to popular belief,
SPICE models can also be bad.

ALSO, contrary to popular thinking among process and/or chip
designers, the voltages on the pins/pads of the buffers WILL
go outside the supply rails more often than you would want to.
I had numerous situations in my experience when I was told that
those cases don't have to be characterized for normal operation
because they are not supposed to happen. This is partially the
reason why we see SPICE models with such clamping currents.

The bad news is that it DOES happen, and the response of the
system DOES depend on how the devices clamp these currents, so
we DO NEED to model these things accurately.

Of course, in carefully designed (parallel terminated) systems
this may not occur at such large amplitudes. Also, at very low
voltage swing signaling even a full over/undershoot may not be
large enough to forward bias these clamps, so this problem may
manifest itself in different colors in the not so distant future.

Arpad Muranyi
Intel Corporation

-----Original Message-----
From: Weston Beal [mailto:[email protected]]
Sent: Wednesday, March 15, 2000 3:19 PM
To: [email protected]
Subject: RE: [SI-LIST] : Bad IBIS models!



Also, curve values should be reasonable. A clamp diode doesn't pass
12.3487E+23 A, but I see this in IBIS file all the time. Details like this
cause me to doubt the integrity of the whole file.


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