From: mjs ([email protected])
Date: Fri Mar 17 2000 - 08:29:33 PST
Let's assume that a power subsystem has a low, flat impedance up to a few
hundred MHz, and has a pair of realtivly unbroken planes. Only problem is
that the stackup is s-G-s-s-P-s since the engineer has insisted that EMI
will be a problem unless all noisy digital signals are 'sandwiched'
between the planes. This board also has parts with 1-2ns edge rates.
I am arguing that s-s-G-P-s-s is the preferred stackup, as this would
allow the planes to be 4-5mils apart instead of 40mils on an .062" card,
yielding much greater plane capacitance.
My questions is this: How does a lack of planar capacitance contribute
to increasing EMI? It seems that not having the proper plane capacitance
would tend to slow edge rates and possibly be one of the lesser SI sins.
Also: Is there any validity to the s-G-s-s-P-s 'copper sandwich'
PCB Design Engineer
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