From: [email protected]
Date: Tue Mar 14 2000 - 15:14:49 PST
There are some other techniques to solve the dead band
problem. among them a fully balanced diffferential PLL will
do a good job. Several ten ps jitter should not be a problem.
As mentioned by someone in this forum, if the bandwidth
of the PLL is much larger than the SSC frequency it will not
cause too much trouble in phase jitter. Depending on the
jitter requirement and PLL design, I would say a ratio of 100
between the bandwdith and the SSC frequency would
probably be O.K..
Other than ICS, there are some other vendors in the market,
including us. (Of course, no commercial :-).)
sweir <[email protected]> on 14/03/2000 17:55:11
Please respond to [email protected]
To: [email protected]
cc: (bcc: Raymond Leung/QSA/AU)
Subject: Re: [SI-LIST] : SSC
SSC synthesizers modulate the clock output frequency at a fairly low rate
in order to spread the frequency spectra of the clock. Since the EMI
energy that is constant is now spread over a wider band, the peak level
falls. This can buy several db improvement.
The PLL must stably track the bandwidth of the SSC clock source without
gaining or losing more phase than allowed for in the timing budget. Be
careful if the PLL uses a phase-frequency detector, as these devices have a
gain dead-band at zero error that causes phase jitter. A typical fix is to
bias the error amplifier with a little DC, so that they do not quite get to
zero error. However, when you use an SSC, the loop gets pushed around a
little, and depending on the coefficients could push the part back into the
ICS( Cypress ) among others build these things.
At 03:09 PM 3/14/00 +0800, you wrote:
>What is a Spread Spectrum Clock synthesizer and why it is used in PC
>motherboards? What are the limitations when chosing a PLL for the Registered
>DIMM if you need to support SSC? Do you know of any such chips?
>With best regards,
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