Re: [SI-LIST] : 2 Layer Boards and Ground Grids

About this list Date view Thread view Subject view Author view

From: [email protected]
Date: Tue Mar 14 2000 - 09:28:21 PST


David,
We are using two-layer cards on network adapters, with clock speeds up to 50MHz,
with no problems. We use Spread Spectrum Clock Generators (SSCG's) wherever we
can to broaden/lower radiated emissions, because they are much cheaper than
adding power/ground planes to the cards. Your power and ground grids will need
to occupy both sides of the card, vertical traces on one side and horizontal
traces on the other, following the same X-/Y-scheme as you use for the signal
wiring.

Our groundrules are:
1. Ring the card on both sides with ground. Tie these rings together with vias
spaced no more than 0.5" apart. Irregular
     spacing of the vias is better than uniform spacing. Power/signal wiring
that extends past the ground grid may act as
     a monopole antenna on a ground plane at some frequency-- probably one that
we don't want!
2. Put vertical ground/power traces on one side of the card, and horizontal
ground/power traces on the other side,
     paralleling your signal wiring.
3. "Sketch in" the ground/power grids before running critical traces. If your
power is well bypassed, you can run a clock
     trace in between power and ground to give you the effect of guard traces
without costing you board space. These
     power and ground traces will need vias to change direction everywhere the
signal trace has vias to change direction.
     We usually put grounded guard traces around clocks and other critical nets,
that completely encircle the clock net
     on each layer (except, perhaps, at the very ends connecting to the driver
and receivers), with vias carrying the
     guard net between layers everywhere the clock net changes layers.
4. For pin-through-hole (PTH) components, try to run a pair of traces
(horizontal & vertical) through each ground/power
      pin. Put a bypass capacitor close to each power pin.
5. For surface-mount-technology (SMT) components, put bypass capacitors very
close to the power pins and their
      associated ground pins, closer to the power pins if you have a choice.
(The ground grid usually has lower
      impedance than the power grid.) Run the ground/power traces through the
SMT pads if you can. Otherwise use a
      short/fat trace (say, < 0.25" long and >= 0.024" wide) to connect the
ground/power pin to the bypass capacitor and
      to a via that has horizontal & vertical traces going to it.
6. Try to have at least two traces going to every ground/power connection. I
get nervous if I have an isolated ground/
      power trace longer than about 0.5".
7. If you have to have a "hole" in a grid, perhaps for a component that uses a
different supply voltage, try to circle it with
     at least two traces on each side with frequent cross-links.
8. Fatten the main ground/power traces to 0.050" where possible, or as wide as
you can. Make connections to
     components 0.024" wide if you can (this also helps you distinguish signals
from ground/power connections when
     you are looking at the card).
9. Tie the horizontal and vertical traces together with vias everywhere you
can. My usual goal is to have a grid with no
     holes bigger than 0.5" x 0.5". This is tight enough that we don't have to
run ground/power traces next to each other.
10. Sneak extra ground/power wires through anywhere there is room. Trace
inductance dominates trace resistance
     once you get above a megahertz or so, and is proportional to
log(length/width). Thus an 0.006" trace will do almost
     as much good as an 0.050" trace would in terms of reducing L * dI/dt drops.
Tie these together with vias if you can,
     but if you can't, just having the wires in that section of the grid will
help.
11. Fatten up ground as much as you can using ground fill.
12. If you have a ground patch bigger than about 0.25" x 0.5" with only one
wire or via going to it, either add one or more
       connections to that patch (preferred) or shrink it. The capacitance of
these almost-isolated patches can resonate
       with the wiring inductance, causing them to act as antennas.

                                                   John Barnes Advisory
Engineer
                                                   Lexmark International

**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:35 PDT