From: Greim, Michael ([email protected])
Date: Mon Mar 13 2000 - 05:06:42 PST
I think that looking at ratios is the wrong way to go. I
prefer to look at the absolutes of the situation, in which
case you are comparing apples and potentially watermelons
from an implementation standpoint. As you have not
told us much about your system, I will have to proceed
with some assumptions.
If you are proceeding with a dual stripline implementation,
driving conventional technology (LVTTL and such) a wide
trace is going to offer you a very small impedance unless
your spacing to the planes is very large. If you are targetting
a conventional .062 thick board (as recently discussed) you
will quickly find that you will not have many routing layers.
Secondly, with a 10 mil line and 20 mil space, you are eating
up a bunch of routing channels on the board that may cause
your layer count to increase, especially if you are looking to
fan out some fine line BGAs.
I would advocate going with the smaller trace, and if you
really do have the room for a 10/20 scheme then increasing
the space gap between your 5 mil traces for less cross
talk. As others have mentioned, I think some of the other
issues that may play a larger role in your SI solution are
your decoupling strategy and return paths within the board.
And all this science they don't understand
It's just my job six days a week.....
The time is gone, The email's over, thought I'd
something more to say.........
Michael C. Greim Consulting Engineer
Mercury Computer Systems, Inc email: [email protected]
199 Riverneck Road V: 978-256-0052/x1607
Chelmsford, MA 01824-2820 F: 978-256-4778
> -----Original Message-----
> From: [email protected] [SMTP:[email protected]]
> Sent: Sunday, March 12, 2000 8:05 PM
> To: [email protected]
> Subject: [SI-LIST] : trace width for clock routing- wider/narrower?
> Dear All SI experts,
> For clock routing, does wider trace width have more advantage than
> narrower one ,in term of better electrical properties, under the condition
> of same trace to space ratio and good match in impedance with source
> For example, 5 mils trace width with 10 mils trace spacing versus 10mils
> trace width with 20 mils trace spacing.
> Thank you for your helps in advance.
> John Lin
> SI Engineer
> Quanta Computer Inc.,Taiwan, R.O.C.
> Email: [email protected]
> Tel: 886+3+3979000 ext. 5183
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