Re: [SI-LIST] : ESR and bypass caps

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From: Scott McMorrow ([email protected])
Date: Sun Feb 06 2000 - 22:15:43 PST


The links on you page are wrong.

There is a backslash instead of a forward slash in
the links to the presentations and to the tools.



Istvan NOVAK wrote:

> DougS,
> As Ray pointed out, Larry's deck was for the single-node analysis. To
> illustrate the effect of capacitor locations, I compiled a short slide show
> from various simulation results, it is posted in
> under illustration tools. On each page
> there are self-impedance profiles of a 8"x8" plane pair with 2-mil FR4
> dielectrics, with four different conditions: 1) bare planes, 2) 0.1uF bypass
> capacitors all in the center, 3) the same number of 0.1uF bypass caps spread
> evenly around the board periphery, and 4) the same number of resistive
> termination evenly spread along the board periphery. From the many
> simulated scenarios probably these four represent the most interesting
> extreme corners. The impedance on a one-inch grid was simulated between the
> planes and the impedance magnitudes are plotted in ohms. The successive
> pages correspond to different frequencies. Note that here no attempt was
> made to smooth out the impedance profile by selecting a range of capacitance
> values, instead the emphesis was on the variation with capacitor location.
> Istvan Novak
> SUN Microsystems

Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231

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