RE: [SI-LIST] : interplanar capacitance

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From: Harris, George ([email protected])
Date: Thu Feb 03 2000 - 14:17:53 PST

Remember that you must provide a low impedance return path for the signal
current. If your signals are driven by a mix of 3.3v and 5v chips, the
stackup you show is just fine. Keep the 3.3v signals between ground and the
3.3v plane, and the 5v between the 5v and the other ground plane. With this
stackup you don't have much interplanar capacitance but the need to keep
return loops at low impedance outweighs this consideration. Just use more
h-f bypass caps.
If however all your signals are driven from only one of the voltages, then
using the stackup where power/ground planes are adjacent may be better,
although you will have more crosstalk in the dual stripline configuration.

George Harris
Tel: 508-467-8893
[email protected] <mailto:[email protected]>
COMPAQ Computer Corporation


-----Original Message-----
From: Speer, Ewart [mailto:[email protected]]
Sent: Thursday, February 03, 2000 2:49 PM
To: '[email protected]' <mailto:'si-lis[email protected]'>
Subject: [SI-LIST] : interplanar capacitance

Dear List Members,

I have an eight layer board with four routing and four plane layers. The
stackup I have chosen is;
        Primary side (signal) - contains all components
        +5V (full plane)
        Internal (signal)
        GND (full plane)
        +3.3V (full plane)
        Internal (signal)
        GND (full plane)
        Secondary side (signal) - no components

I want to take advantage of the interplanar capacitance between planes GND
and +3.3V. What core thickness should I specify? At what dimension
(thickness of core) would I lose this advantage? Also, on the secondary
side under an FPGA I have a large copper fill area that carries +2.5V, can I
use the adjacent GND plane and this area fill for more decoupling. If so
what thickness of prepreg should I specify? I would like to maintain a
0.062" overall thickness of the PWB.

Thank you all,
Ewart Speer
Scientific Atlanta

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