**From:** Mike LaBonte (*[email protected]*)

**Date:** Thu Jan 20 2000 - 05:55:19 PST

**Next message:**zanella, fabrizio: "RE: [SI-LIST] : **error**: internal timestep too small"**Previous message:**[email protected]: "[SI-LIST] : differential trace model (was: receiver jitter)"**In reply to:**Chris Cheng: "[SI-LIST] : receiver jitter"

Some food for thought about receiver characterization:

When modeling a driver, we produce separate model data for process

corners such as fast, typical, and slow, which represent points on

some distribution. This is essentially because our simulators only

simulate a single voltage at each node, not a voltage probability

distribution over time. However, we do not necessarily have the

same limitation with receivers.

One *can* model a receiver as a sense amplifier and comparator

circuit, and give it process corners like the driver. But a behavioral

receiver model could also utilize probability. At any point in time,

there is a probability that the output is high, and a separate

probability that the output is low. For those desiring a simple

binary result, the output "is high" when the high probability

exceeds the low probability. For more sophisticated analysis one

would choose a required confidence level and look for the point

in time where the "right" state reaches a corresponding probability.

Failure analysis would look for the "wrong" answer to exceed some small

probability within a critical time range.

Sound too complicated? Maybe. Ease of model creation is always a key

point to consider. I am not convinced that creating fast/typical/slow

models for a receiver is much easier than creating a probability

function, however. In fact, I haven't yet seen much discussion

about how receiver models would be created, regardless of the type of

model.

As for the benefits, this may be the right way to characterize

"jittery receivers". Plus, it may eliminate the need to iterate

over driver/receiver process corner combinations (fast/fast, slow/slow,

typical/typical, fast/slow, slow/fast, etc.), saving some simulations.

This is because the earliest and latest possible switch times can be

determined at each receiver, in one simulation.

I will omit the discussion of how the model data might be conveyed,

except to say that the first possibility that comes to my mind is

a circuit model where 2 output voltages fall between 0V and 1V,

representing high and low probabilities.

Mike

Chris Cheng wrote:

*>
*

*> as core and signal swing getting smaller and smaller, this
*

*> problem is getting worst. compound this with source sync
*

*> buses where the strobes and data can behave differently
*

*> (true differential vs. pseudo differential), i believe
*

*> predicting the response of the receiver under different
*

*> waveforms input will be as important as simulating
*

*> the propagation of signal in the interconnect
*

*> environment. this will be the final nail in the coffin for
*

*> behavioral models like ibis which is totally incapable of
*

*> handling such analysis. i have seen pitiful attempts to
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*> qualitatively describe it in ring back or edge rate
*

*> extrapolation but without the ability to simulate the
*

*> receiver behavior, those specs are just fancy words with
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*> no meaningful insight into the response of the true
*

*> receiver.
*

*> can i spell SPICE again.
*

*> chris
*

*>
*

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**Next message:**zanella, fabrizio: "RE: [SI-LIST] : **error**: internal timestep too small"**Previous message:**[email protected]: "[SI-LIST] : differential trace model (was: receiver jitter)"**In reply to:**Chris Cheng: "[SI-LIST] : receiver jitter"

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