[SI-LIST] : Zo Variance From Plating Thickness Variation

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From: Dave Hoover ([email protected])
Date: Fri Jan 14 2000 - 10:48:32 PST

Michael wrote.....

Dave [Groovy]: you're one SI'er who is intimately familiar with real world
PWB fab variances. Have you ever seen application problems that were due to
unevenness of finished trace geometry?

Michael Alderete

Michael [;-) Rut Oh..the secrets out]:

Honestly I haven't heard of any issues popped up in the field from
unevenness of finished trace geometry. My Industry Specs (IPC-6012)dictate
minimum copper thickness. If we have a process related issue that would
reduce the copper thickness below the values required we would generally
cull that out during cross section analysis. Also we would see it in the
Zo (and/or Zdiff) TDR results. Isolated spots (like major copper pitting)
would be highly visable and rejected at inspection.

From an electrical standpoint, I haven't heard of any of our current
who have had risetimes (and fall times) short enough to really see issues
minor plated copper variance. (Now if I was building microwave stuff I may
have had a different answer to this.....)

David Hoover

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