Re: [SI-LIST] : STTL3 bus terminations

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From: D. C. Sessions ([email protected])
Date: Mon Jan 10 2000 - 14:00:01 PST

Yann Noury wrote:

> We are working about connecting a STTL3 class II compliant SDRAM (
> SAMSUNG 64MB) to an Altera APEX 20K400E PLD, which
> provides STTL3 class II compliant block IO's.

Class II is intended for use in bidirectional interconnect (e.g. SDRAM
data busses). Class II drivers are sized to drive a 50-ohm line
through 10-ohm stub dampers into a line terminated at each end with
50 ohms to Vtt.

> I have found the JEDEC standard ( EIA/JESD8-8 ) , but it describes the
> termination only for
> unidirectionnal signal.
> it is describing in the attachment:
> the scheme shows an output buffer connected to a bidirectionnal buffer !
> How does it work ???
> I would like to find the proper terminations for bidirectionnal signals
> such as Data signals with 50 Ohms lines .
> I have the same problem for LVDS IO's, for bidirectionnal signals !

If your line impedance is 50 ohms (not a given, btw) then you can get
reasonable signal quality with a 50 ohm terminator to Vtt at each end
of the line and 10-ohm stub dampers at each memory device. The
controller is a bit of a special case, since it's usually alone and
distant from the memories and doesn't need a stub damper. For the
controller you may want a larger launch voltage to compensate for the
RC delay effect of several physically close memories at the other end
of the line on write cycles.

A higher line impedance is a bit of a tradeoff. You get a more launch
voltage but the loading degradation is greater.

D. C. Sessions
[email protected]

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