Re: [SI-LIST] : Input switching threshold & CPCI

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From: D. C. Sessions ([email protected])
Date: Thu Jan 06 2000 - 11:09:59 PST

"Ingraham, Andrew" wrote:
> >> >> The "VCC5REF" node is suspicious ... what would this be for in
> >> a
> >> >> 3.3V PCI signaling environment?
> >> >
> >> >High-side clamping. 5-v tolerant 3.3v devices need to bias the N-well
> up
> >> >to 5 volts to keep the parasitic drain-well diodes of the P-channel
> devices
> >> >from forward-biasing. (The gate logic behind them is -- ahem! --
> exotic.)
> >>
> >> Well, then this IS a "5V" PCI device (despite making use of 3.3V power),
> and
> >> the 0.8V, 2.0V input thresholds ARE the correct ones.
> >
> >Not really. ...
> If it has a way to not clamp to 3.3V on a 5V bus, AND to clamp to 3.3V on a
> 3.3V bus, then it's OK, and I guess it should have TWO different IBIS spec
> sheets covering the two cases.

Agreed. For one thing, the P-channel drive varies somewhat with well bias.

> But if it is simply 5V-tolerant, all the time, then it can't be used on a
> 3.3V bus. I thought that was the case with this part (with its VCC5REF pin
> ... unless that pin is part of an adjustable clamp and is connected to the
> PCI bus's +Vi/o pins).

Can't speak for others, but that's how ours works (well bias goes to VIO)

D. C. Sessions
[email protected]

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