From: Hank Zauderer ([email protected])
Date: Tue Jan 04 2000 - 17:03:03 PST
Please contact me for details on the following SI Manager opportunity:
As Manager of a Hardware Design Verification group, you will build and
manage a team responsible for signal integrity and timing analysis of board
and system-level designs for enterprise class file servers and Internet
caching appliances.
Specific Responsibilities:
Work with Design Engineers, EMC Engineers, and PCB Layout Engineers to
architect and design products based on the latest generation microprocessor
and I/O technologies. Work with the most advanced signaling technologies,
ranging from 1000Base-T Gigabit Ethernet, 1 and 2 Gb FibreChannel, 300 MHz
CPU buses of the Alpha 21264/21364 and Intel CPUs, and future I/O
technologies, including System I/O (NGIO + Future I/O). Define the design
verification process and select the appropriate tools.
Skills and Qualifications:
BSEE (or related) required, MSEE desired, with 3+ years of management
experience. Proven track record of recruiting and retaining world class HW
engineers. Excellent written and verbal communication skills with those less
knowledgeable in this area. Good project planning and time management
skills. Expert in HW design methodologies for high-speed system design.
Excellent working knowledge of signal integrity and other high-speed design
issues in PCBs. Working experience with XTK, SPICE, 3D field solvers, static
timing analyzers highly desired. Working experience with gigahertz signaling
highly desired.
Contact:
Hank Zauderer ([email protected])
Operational Consulting Group
(831) 662-0605
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