From: [email protected]
Date: Fri Nov 05 1999 - 09:47:44 PST
Hi folks,
first, thanks for the suggestions about what to do with the micro noise.....
We have some things to try, I'll share what I find out.
One of the things I'd like to try is arranging the PWB layers a little
differently.
I have a 4 layer board ( I have no say, as usual ), The first design was
stacked:
Layer 1 Component, Pads, some routing.
Layer 2 Power
Layer 3 Ground
Layer 4 Routing
I'm not keen on this arrangement because traces ( including addres/data etc.
) are forced to go from layer 1 to 4 to get from A to B. I believe passing
any trace trough a plane should be avoided if possible...... Even though I'm
only running a 50 MHz clock! So, what if I do this?:
Layer 1 Component, Pads, some routing.
Layer 2 Routing
Layer 3 Ground
Layer 4 Power
Thoughts why I suggest this:
1) I have to have all parts on the top surface, hence must have pads there.
2) I have to have some 200 test points on the lower surface, if this were
ground plane, I'd carve it up big time. I believe that I'd rather have ground
on Layer 3 and more intact, since the chips can have a decoupling cap sharing
the power pin pad to make up for crappy power plane.
3) By making Layer 3 ground, the traces keep closely coupled, faster traces
will route layer 2 to increase this effect.
4) The card adjacent to layer 4 is an I/O card, it has Fast Transient Burst
noise up to 4 kV, and could carry switching noise out on wiring. The
ground/power layers will help shield layers 1 and 2 from this.
I've not seen this lay-up suggested much, but it looks like it could work. So
before I go ahead and try it I thought I'd bounce the idea.....
Opinions?
Thanks,
Derek.
**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:38 PST