Re: [SI-LIST] : [Fwd: Majordomo results: Looking for highspeed buffer parts]

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From: [email protected]
Date: Thu Nov 04 1999 - 21:43:19 PST


Jason,

My personal view only:

Steve is right that the part is not fast enough for you. Besides, you may not
be happy with 500ps skew among the outputs

Raymond

---------------------- Forwarded by Raymond Leung/QSA/AU on 05/11/99 15:43
---------------------------

sweir <[email protected]> on 05/11/99 12:20:03

Please respond to [email protected]

To: [email protected]
cc: (bcc: Raymond Leung/QSA/AU)

Subject: Re: [SI-LIST] : [Fwd: Majordomo results: Looking for highspeed buffer
      parts]

Jason,

Be careful if you intend to use an inverter as a clock buffer. The alvc
stuff is pretty fast, but not nearly fast enough for your needs. That
particular part is about 4nS spec into a heavy load, and a minimum Tpd spec
of 1nS. At 240MHz Tpd alone is 50% of your cycle interval. That
translates to linear amplifier. I don't know who did your ASIC's or the
system design, but 240MHz at SSTTL is going to be very hard to do.

One of the HSTL, or GTL variants is a much better choice, or alternatively
distribution of a lower frequency clock with PLL's inside each chip
multiply up to the necessary value. If you have already committed the
ASIC's this could be a problem.

Go look at Lattice Semiconductor for the 3nS GAL, GAL16LV8.

Regards,

Steve.

At 07:17 PM 11/4/99 -0800, you wrote:

>Steve,
>
> Thank you very much for the reply!
>
> The 240 Mhz part is to buffer the clocks from clock synthesizer
>to multiple ASICs as a clock source. The ASICs have 3.3v IO but
>are 5V tolerate. I saw and IDT part# IDT74ALVC16244A that may
>be promising. Have you had any experience with that part?
>
> Do you know of any GaAs vendor that may provide faster
>parts for my needs? I wonder what people use for buffering
>the clocks for AMD's 200 Mhz system clock or DDR clocks?
>
> Can you give me a pointer for the GAL part#/vendor info?
>
> Thanks in advance!
>
>-Jason
>
> >
> > From your post, I guess that you want 3.3V SSTTL levels. 240MHz is really
> > beyond any practical upper limit for SSTTL. There isn't much out there that
> > can reliably get below a Tpd of 1.5nS, which would typically be suitable to
> > 150-166MHz at the high-end. If you want to reach beyond 200MHz, it is time
> > to use low-swing logic.
> >
> > The application sounds like a phase-splitter. If it is, instead of an
> > inverter try a precision delay line, either buried in etch, or off the
> shelf.
> >
> > The 120MHz mux / FF can be implemented in either a 5nS or 3nS GAL. Which
> > grade is appropriate depends on the specifics of your Tsu and Th
> > requirements.
> >
> > Regards,
> >
> > Steve.
>
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