From: Larry Miller ([email protected])
Date: Wed Nov 03 1999 - 06:09:04 PST
Excellent comments.
Larry Miller
At 02:12 PM 11/2/99 -0800, you wrote:
>Paul,
>
>Thanks for the article. I think that the article could be better
>written. I believe that Mr. Ritchey's basic premise is that for a
>significant class of designs where the signals are completely contained
>within the PCB, and do not cross any moats, the sole benefit of
>differential signaling is improved ground noise immunity at the
>receiver. What he appears to leave out of the article are the
>parametric
>limits involved. I am fairly unhappy with those omissions and the
>writing
>style in general, but I am relatively sure that Mr. Ritchey knows what
>he
>is talking about.
>
>Important items either missing, or missing emphasis in the article.:
>
>1. The weak coupling, 10-15% between the two signals in a differential
>pair translates to a fundamental requirement to treat each of the two
>signals with the same care and feeding as two independent single-ended
>signals of like risetime and amplitude. The differential nature of the
>signals within the PCB is not going to significantly help EMI versus the
>two signals taken separately. So long as the signals remain confined to
>the PCB.
>
>2. That only to the extent that some additional timing uncertainty due
>to
>variations in and Tr/Tf are acceptable, the two trace lengths may vary
>from one another.
>
>3. Than in no case should the trace lengths be allowed to vary by more
>than the lesser of the minimum Tr or Tf.
>
>4. That the high sensitivity of the differential receiver comes at a
>price. Any differential noise on the pair from an aggressor will shift
>the
>switching point in time, or may even cause a double-transition in the
>receiving output. This is a very good reason to keep the pair together,
>and away from aggressors such as TTL/CMOS. This is independent of
>whether
>lead lengths are matched or not.
>
>5. Since the signals will each independently reflect mostly from the
>nearest ground plane, matching vias between the ground plane(s) and each
>of
>the signals is more significant than matching vias between the two
>signals
>when switching layers.
>
>I disagree with his characterization of an emitter-coupled differential
>amplifier as a "current switch". A diff amp is a diff amp. It
>definitely
>has a linear region, and the output slew rate definitely depends on the
>amount of overdrive at the input. When one of the wavefronts arrive at
>the
>receiver delayed, the switching point moves up or down referenced to
>ground. Assuming perfectly trapezoidal source signals, the crossover
>point
>in time is delayed:
>
>Tdelay = ( Tslew + Toffset ) / 2
>
>Where Tdelay is the crossover point at the receiver, Toffset is the time
>offset in the signal pairs, and Tslew is the slewing time of either
>signal,
>presumed to be equal for both.
>
>If the signals are perfectly trapezoidal, and the amplifier is perfectly
>linear throughout its common mode region, then Tdelay is constant for a
>given Toffset. And, Toffset may be varied up to, but no more than
>Tslew. ( If the value approximates or exceeds Tslew, timing can become
>very erratic. ) However, neither assumption holds absolutely in
>real-life. The result is some loss of symmetry, and introduction of
>jitter.
>
>How bad can any of this be? Given that Mr. Ritchey advocates limiting
>Toffset to 1/3 Tslew, the Tdelay will be no more than Tslew / 6. The
>additional jitter and loss of symmetry will be some fraction of this
>number
>due to non-linearities in the source signals, and the receiving
>amplifier
>response. The switching point voltage moves by ( Vhi - Vlo ) / 6 or
>less. The signal crossover point now lies between 33% and 67% as
>compared
>to an ideal of 50%. It would take a good number of very careful
>measurements to determine what the delay sensitivity to the common mode
>switching point is. Perhaps someone would like to do a paper on this.
>
>The total distortion is likely to come-out quite small. Whether or not
>it
>matters depends on the application circuit. For instance, a Channel
>Link
>type device at the upper clock rates has timing margins in the 10's of
>pS. In such a case, the recommended technique could be a real problem
>if
>taken to the limits recommended.
>
>As I have said before, I disagree with his categoric statement that the
>total impedance is just the single-ended impedance divided by two. That
>statement ignores the mutual coupling of 10-15%, so I expect a 5-8%
>calculation error.
>
>In the end, I believe that the article could have been written better.
>For
>a number of cases, I believe the article's intent is valid within the
>confines of a PCB. I do not agree at all with this method for any
>signals
>which leave a box, as the offset dramatically increases common noise
>which
>is likely to become an emissions nightmare.
>
>Regards,
>
>
>
>Steve.
>
>At 08:04 AM 10/29/99 -0400, you wrote:
>> It is also stated in this article that critically matched
lengths is
>>unnecessary, however you MUSt take into account your noise margins(parallel
>>aggressors). It states that differential transmissions only need about 15mV
>>difference to switch.
>> Assuming no noise/ crosstalk and a 300pSec rise time in FR-4(180
>>pSec/In), the pairs length could be mismatched by as much as 1.6
>>inches(Tr/Td) and still function. So a 500 mil difference in line length
>>would be acceptable. What he is really stating is that if you need to route
>>one of the traces around a through hole, just do it.
>>
>> It only shows an example for ECL and LVDS Logic in the acrticle.
>>
>>Regards,
>>
>>Paul Denomme
>>
>>
>> > -----Original Message-----
>> > From: S. Weir [SMTP:[email protected]]
>> > Sent: Thursday, October 28, 1999 6:04 PM
>> > To: [email protected]
>> > Subject: RE: [SI-LIST] : Comments from your SI seminar (SendII)`
>> >
>> > Paul,
>> >
>> > Are you assuming:
>> >
>> > 1. The traces have been specified to remain at a constant separation?
>> > 2. The trace pair will have a minimum separation from parallel
aggressors?
>> > 3. The traces will have matched lengths?
>> >
>> > I am not sure how such things can be assumed and make it to the physical
>> > design. If the trace lengths don't match, the signal will have lots of
>> > common mode for fast enough edges. If there is not enough separation
from
>> >
>> > parallel aggressors, then aggressors can inject differential mode
>> > noise. If the traces do not maintain a constant separation, the
impedance
>> >
>> > will vary by about half the variation in the coupling coefficient.
>> >
>> > Regards,
>> >
>> >
>> > Steve.
>> >
>> > At 03:30 PM 10/28/1999 -0400, you wrote:
>> > > I have read an article recently that states that the use of
>> > >specifying the differential impedance of two traces on a circuit
board is
>> > >unnecessary. The only thing you need to worry about is the individual
>> > trace
>> > >impedance. If you need a differential impedance for two lines to be 100
>> > >ohms, just use two 50 ohm lines rather than using two signals whose
>> > >differential impedance is 100 ohms. Also when connecting a 110 ohm
>> > twisted
>> > >pair to PCB you should just connect it to two 55 ohm traces to achieve
>> > the
>> > >110 ohm differential impedance. I have done enough research to draw my
>> > own
>> > >conclusions, but I would like to get the reaction from people in this
>> > forum
>> > >regarding this issue.
>> > >
>> > >Thank you,
>> > >
>> > >Paul Denomme
>> > >Viasystems Inc.
>> > >
>> > >
>> > >
>
>**** To unsubscribe from si-list: send e-mail to
[email protected]. In the BODY of message put: UNSUBSCRIBE
si-list, for more help, put HELP. si-list archives are accessible at
http://www.qsl.net/wb6tpu/si-list ****
>
>
**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:32 PST