From: Miguel Silveira ([email protected])
Date: Mon Nov 01 1999 - 10:21:24 PST
[Sincere apologies if you receive more than one copy of this message -
it is being posted to several mailing lists. Please forward to
anyone you think might be interested]
===> Early Deadline for Registration (reduced fees!!) is October 31st
As General Chair of VLSI'99, I would like to invite you all to attend
VLSI'99 next December (1st - 4th) in Lisbon, Portugal. Details of the
technical program are given below, as well as the social program,
registration and hotel reservations.
Thank you for your attention and looking forward to your participation,
-Miguel Silveira
VLSI'99 General Chair
-------------------------------------------------------------------------------
Assistant Professor, ECE Dept. [email protected]
IST - Instituto Superior Tecnico, Technical University of Lisbon
INESC - Systems and Computers Engineering Institute
Rua Alves Redol, 9, 136, 1000 Lisboa, PORTUGAL
Phone: + 351 1 3100337 Fax: + 351.1.3145843
-------------------------------------------------------------------------------
Please find attached the final program for VLSI'99, the X IFIP
International Conference on Very Large Scale Integration
Best Regards,
-Miguel Silveira
VLSI'99 General Chair
CALL FOR PARTICIPATION
----------------------
VLSI '99
X IFIP International Conference on Very Large Scale Integration
Meridien Park Atlantic, Lisbon, Portugal
December 1-3, 1999
Main Sponsors: IFIP - International Federation for Information
Processing
INESC - Systems and Computer Engineering Institute
Proceedings published as a book by Kluwer Academic
INTRODUCTION
------------
VLSI '99, the tenth biennial international conference on Very Large
Scale Integration Systems and their design, sponsored by IFIP TC 10
Working Group 10.5 (VLSI) will take place at the Meridien Park Hotel
in Lisbon, from December 1st to the 3rd.
The X IFIP International Conference on Very Large Scale Integration
provides a forum for the presentation and discussion of the latest
advances and solutions the problems arising in the design and
verification of todays complex VLSI designs and Systems on a Chip.
Improving designer productivity requires the development of new tools
and techniques, increasing the abstraction level of designs and
introducing reuse of components and systems parts.
The conference is aimed at bringing together researchers and engineers
from industry, academia and government laboratories from around the
world to address all current and future issues affecting the design of
VLSI systems and Systems on a Chip.
CONFERENCE WEB PAGES
--------------------
Updated information on the conference can also be found on the
conference web pages:
TECHNICAL PROGRAM
-----------------
The Technical Program Committee, composed of over one hundred well
renowned experts from academia and industry from all over the world,
has put together a very interesting technical program which can be
seen at
http://algos.inesc.pt/vlsi99/tech-program.html
The Keynote Address will be given by Dr. Benny Madsen, Technical
Director of Wireless Communications at National Semiconductor
Corporation.
The conference is organized into two paralel tracks that include
twelve regular paper sessions covering broad topics such as:
- Analog Systems Design and Modeling
- Image Processing
- Reconfigurable Computing
- Memory and System Design
- Low Power Design
- Test, Simulation and Verification
- Analog CAD and Interconnect Modeling
- CAD for Physical Design
- High-level Synthesis and Verification of Embedded Systems
In addition, five special session were prepared to address important
topics such as
- Microsystems Design
- RF Design and Analysis
- Reconfigurable Hardware Systems
- Architectural Synthesis and Verification
- Timing and Verification
Three embedded tutorials are also being offered to all participants at
no extra charge. The tutorials are given by well known experts in the
field and cover important topics such as
- CAD for Microelectromechanical systems
- Interconnect Process Parametrization
- Design of Video Systems on Chip
Detailed information on the technical program is included at the end
of this message. All information is available in the conference Web
pages.
REGISTRATION INFORMATION
------------------------
Registration information, including a registration form can be
downloaded from
http://algos.inesc.pt/vlsi99/registration/registration.html
Anyone experiencing any difficulties should contact the Conference
Secretariat.
VLSI'99 Conference Secretariat
INESC
R. Alves Redol, 9
1000 Lisboa
Portugal
Tel: +351-1-3100337
Fax: +351-1-3145843
e-mail: [email protected]
Once filled the registration form can be faxed or mailed to the
Conference Secretariat.
Reduced early registration rates are available until the end of
October. Reduced fees are available for IFIP and IEEE members as well
as students.
Applicable fees for member or non-member cover one copy of the book
containing the technical digest of VLSI'99, attendance to all
technical sessions, tutorials, lectures, coffee breaks, lunches and
one entrance to the conference banquet. Student registration covers
all of the above with the exception of the banquet. Extra tickets for
the banquet can be purchased separately, subject to availability.
HOTEL INFORMATION
-----------------
The conference will be held at the Hotel Meridien Park Atlantic, an
excellent hotel, centrally located in Lisbon with easy access to the
airport and public transportation.
A block of rooms has been reserved at the Meridien at a special rate
for registered conference participants. Reservations at the reduced
rate are guaranteed until the end of October. For reservations
we encourage you to download the hotel reservation form available at
http://algos.inesc.pt/vlsi99/hotel/hotel-reservation.html
and fax it to the hotel at the given number. If you wish to contact
the hotel directly, please be sure to mention you are attending the
VLSI'99 Conference and request the special rate for the conference
Hotel Meridien Park Atlantic
149, Rua Castilho,
1099-034 Lisboa - Portugal
Phone: +351 (1) 381 87 00
Fax: +351 (1) 389 05 05
e-Mail: [email protected]
URL: http://www.portugalvirtual.pt/meridien.lisboa
SOCIAL PROGRAM
--------------
Since all work and no fun makes everyone dull boys or girls (our
little tribute to the late Stanley Kubrick) we have also prepared an
extensive and very interesting social program that includes a
reception, on December 1st, open to all conference participants and
spouses and a banquet the following day. The banquet will take place
in the new Lisbon Oceanarium, the largest in Europe and the main
attraction of the World Expo'98 that took place last year in Lisbon.
A visit to the Oceanarium will be included for all participants.
Tours of the main attractions in Lisbon and its surroundings
(including the beautiful Sintra) are also being setup at this time.
Details will be available in the Conference Web pages. A program for
spouses or accompanying guests will also be available.
We are specially looking forward to your presence at VLSI'99,
hoping that you can accept our hospitality and enjoy a nice Autumn in
Lisbon.
ADDITIONAL INFORMATION
----------------------
Contact the Conference Secretariat or the General Chair and Vice-Chair
GENERAL CHAIR: GENERAL VICE-CHAIR:
Luis Miguel Silveira Jose Carlos Monteiro
Dept. of Elect. and Computer Eng. Department of Informatics
Systems and Computers Research Institute (INESC)
Instituto Superior Tecnico (IST), Technical University of Lisbon
Rua Alves Redol, 9, 136
1000 Lisbon, PORTUGAL
Phone: +351-1-3100337 Phone: +351-1-3100283
Fax: +341-1-3145843
E-mail: [email protected] E-mail: [email protected]
http://algos.inesc.pt/~lms http://algos.inesc.pt/~jcm
See you in Lisbon in December!! Best regards,
-Luis Miguel Silveir
VLSI'99 General Chair
----------------------- Detailed Technical Program follows
--------------------
X IFIP VLSI Conference Program
December 1-3, Lisbon, Portugal
Meridien Hotel
Keynote Address
---------------
New Wireless Connectivity Standards - Enabling "True" Information
Mobility
Dr. Benny Madsen
Technical Director, Wireless Communications
National Semiconductor Corporation
Regular Paper Sessions:
-----------------------
V1 - Analog Systems Design
Optimizing Mixer Noise Performance: A 2.4 GHz
Downconversion Gilbert Mixer for W-CDMA Application
Shenggao Li, Mohammed Ismail
Analog VLSI Lab, The Ohio-state University, OH, USA
An analog Non-volatile storage system for audio signals
incorporating signal conditioning for Mobile communication
Devices
Geoffrey B. Jackson, Saleel V. Awsare, Lawrence D. Engh, Peter
Holzmann, Oliver, C. Kao, Carl R. Palmer, Aditya Raina
Information Storage Devices, a Winbond Company, CA, USA
A Design of Operational Amplifier for Sigma Delta
Modulators using 0.35um CMOS Process
Bingxin Li, Hannu Tenhunen
Electronic System Design Laboratory, Royal Institute of Technology,
Sweden
V2 - Analog Modeling and Design
Design of a CMOS Micromixer
Yue WU and Mohammed Ismail
Analog VLSI Lab, The Ohio State University, OH, USA
Nonlinear Analysis of a Short Channel CMOS Circuit for Front-end
RFIC
Yue WU and Mohammed Ismail
Analog VLSI Lab., Department of Electrical Eng., Ohio State Univ.,
OH, USA
On Fast and Accurate Parametric Modeling of Contact to Substrate
Coupling in VLSI Circuits
Nasser Masoumi, Mohamed I. Elmasry, Safeiddin Safavi-Naeini
Department of Electrical and Computer Eng., Univ. of Waterloo,
Canada
High Current Low Voltage Current Mirror
S. S. Rajput, S. S. Jamuar
Department of Electrical Engineering, Indian Institute of Tech.,
India
V3 - Image Processing
A Feature Associative Processor for Image Recognition based on
A-D merged Architecture
Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda,
Mitsuru Homma, Hiroto Higashi and Takashi Morie
Faculty of Electrical Engineering, Hiroshima University, Japan
Massively Parallel Intelligent Pixel Implementation of a Zerotree
Entropy
Video Codec for Multimedia Communications
A.M.Rassau*, G.Alagoda, D.Lucas, J.Austin-Crowe, K.Eshraghian
Centre for Very High Speed Microelectronic Systems,
Edith Cowan University, WA, Australia
*Department of Cybernetics, University of Reading,
Whiteknights, Reading RG6 6AY, UK
Implementation of a Wavelet Transform Architecture for Image
Processing
Camille Diou, Lionel Torres, Michel Robert
LIRMM, Universiti Montpellier II, Montpellier, France
V4 - Reconfigurable Computing
Scalable Run Time Reconfigurable Architecture
Abdellah Touhafi, Wouter Brissinck and Erik Dirkx
Vrije Universiteit Brussel, Brussel, Belgium
Frontier: A Fast Placement System For FPGAs
Russell Tessier
University of Massachusetts, Amherst, MA, USA
Dynamically Reconfigurable Implementation of Control Circuits
Nuno Lau, Valery Sklyarov
Dept. de Electrsnica e de Telecomunicagues da Univ. de Aveiro,
Portugal
V5 - Memory and System Design
An IEEE Compliant Floating Point MAF
R. V. K. Pillai, D. Al-Khalili* and A. J. Al-Khalili
Concordia University, Montreal, Canada
*Royal Military College of Canada, Kingston, Canada
Design and Analysis of On-Chip CPU Pipelined Caches
C. Ninos, H. T. Vergos & D. Nikolos
Computer Technology Institute, Dept. of Computer Engineering &
Informatics, University of Patras, Greece
Synchronous to asynchronous conversion - A case study:
the Blowfish algorithm implementation
Joao M. S. Alcantara, Sergio C. Salomao*, Edson do Prado Granja,
Vladimir C. Alves, Felipe M. G. Franca
COPPE/Federal University of Rio de Janeiro - Brazil
*Military Institute of Engineering - Brazil
Clock Distribution Strategy for IP-based Development
Rui L. Aguiar, Dinis M. Santos
Universidade de Aveiro, D.E.T., Aveiro, Portugal
An Architectural and Circuit-Level Approach to Improving the
Energy Efficiency of Microprocessor Memory Structures
David H. Albonesi
University of Rochester, NY, USA
V6 - Low Power Design
Single Ended Pass-Transistor Logic - A comparison with CMOS and CPL
Mihai Munteanu, Peter A. Ivey, Luke Seed,
Marios Psilogeorgopoulos, Istvan Bogdan
University of Sheffield, E.E.E. Department, E.S.G. Group, United
Kingdom
Multithreshold Technology Low Swing/Low Power Bus Architecture
A. Rjoub, O. Koufopavlou
VLSI Design Lab., Dept. of Electrical & Computer Eng., Univ. of
Patras,
Patras, Greece
Integrating Dynamic Power Management in the Design Flow
Antsnio Mota, Nuno Ferreira, Arlindo Oliveira, Josi Monteiro
IST/INESC, Lisboa, Portugal
Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI
Stefan Lachowicz, Kamran Eshraghian, Hans-Jvrg Pfleiderer*
Edith Cowan University
*University of Ulm
C1 - Test and Verification
The clustering effect on defect-level modeling
Jose T. de Sousa
Bell Labs - Lucent Technologies
FASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC
Circuits
J. Soares Augusto and C. F. Beltran Almeida
INESC/IST, Lisboa, Portugal
Design Error Diagnosis in Digital Circuits without Error Model
Raimund Ubar, Dominique Borrione*
Tallinn Technical University, Estonia
*TIMA-UJF, Grenoble, France
C2 - Analog CAD and Interconnect
Efficient RLC Macromodels for Digital IC Interconnect
Bogdan Tutuianu, Daksh Lehther, Madhulima Pandey, Ross Baldick*
Motorola Inc., Somerset Design Center, Austin TX, U.S.A
*Department of Electrical and Computer Engineering, The
University of Texas at Austin, Austin TX U.S.A
A Decomposition-based Symbolic Analysis Method for Analog
Synthesis from Behavioral Specifications
Alex Doboli, Ranga Vemuri
ECECS Department, University of Cincinnati, USA
A Linear Programming Approach for Synthesis of Mixed-Signal
Interface Elements
Adrian Nunez-Aldana, Ranga Vemuri
Electrical and Computer Eng. Department, University of Cincinnati,
USA.
RF interface design using mixed-mode methodology
A. Gallegos, P. Silvestre, M. Robert*, D. Auvergne*
VLSI Technology, Wireless Communication Research
*Laboratoire LIRMM, CNRS, Universite de Montpellier II, France
C3 - Fundamental CAD Algorithms
Event-Driven Dynamic Minimization during BDD Construction
Rolf Drechsler, Wolfgang Gunther
Institute of Computer Science, University of Freiburg, Germany
AuraII: Combining Negative Thinking and Branch-and-Bound in Unate
Covering Problems
Luca P. Carloni, Evguenii I. Goldberg*, Tiziano Villa+,
Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Dept. of Electrical Engineering and Computer Sciences,
University of California, Berkeley
*Cadence Berkeley Laboratories
+PARADES
Satisfiability-Based Functional Delay Fault Testing
Joonyoung Kim, Joao Silva*, Karem Sakallah
Univ of Michigan, Ann Arbor, MI, USA
*IST/INESC, Lisboa, Portugal
C4 - Verification and Simulation
Verification of Abstracted Instruction Cache of TITAC2: A Case
Study
Tomohiro Yoneda
Department of Computer Science, Tokyo Institute of Technology,
Japan
Speeding Up Look-up-Table Driven Logic Simulation
Rajeev Murgai, Fumiyasu Hirose*, Masahiro Fujita
Fujitsu Laboratories of America, CA, USA
*Cadence Japan, Japan
Using Statistical Stopping Rules for More Efficient Verification
of Behavioral Models
Tom Chen, Isabelle Munn*, Anneliese von Mayrhauser*, Amjad Hajjar
Department of Electrical and Computer Eng., Colorado State Univ.,
CO, USA
*Department of Computer Science, Colorado State University, CO, USA
Embedded Systems Design And Verification: Reuse Oriented
Prototyping Methodologies
S. Raimbault, G. Sassatelli, G. Cambon, M. Robert, S. Pillement, L.
Torres
Laboratoire d'Informatique, de Robotique et de Microilictronique
de Montpellier, Universiti Montpellier II / C, France
C5 - CAD for Physical Design
A Virtual CMOS Library Approach for Fast Prototyping
F. Moraes, M.Robert*, D.Auvergne*,
PUC-RS, Porto Alegre, Brazil
*LIRMM, CNRS/Univ. Montpellier 2, Montpellier, France
RT-level Route-and-Place Design Methodology for Interconnect
Optimization in DSM Regime
Ananth Durbha, Srinivas Katkoori
Dept. of Comp. Science and Eng., Univ. of South Florida, Tampa, FL,
USA
Designing a Mask Programmable Matrix for Sequential Circuits
Fernanda Lima, Marcelo Johann, Josi G|ntzel, Eduardo D'Avila,
Luigi Carro, Ricardo Reis
Universidade Federal do Rio Grande do Sul, Instituto de
Informatica, Porto Alegre, RS, Brasil
Placement Benchmarks for 3-D VLSI
Stefan Thomas Obenaus, Ted H. Szymanski*
School of Computer Science, McGill University, Montreal, Quebec,
Canada
*Communications Research Laboratory, McMaster University, Canada
Substrate Noise: an IC and CAD Designer Perspective
Edoardo Charbon, Joel Phillips*
Cadence Design Systems
*Cadence Berkeley Laboratories
C6 - High-level Synthesis and Verification of Embedded Systems
Architectural Transformations for Hierarchical Algorithmic
Descriptions
Marcio Yukio Teruya, Marius Strum and Wang Jiang Chau
Department of Electronic Enginnering, Escola Politecnica da
Universidade de Sao Paulo, Brazil
An Enhanced Static-List Scheduling Algorithm for Temporal
Partitioning onto RPUs
Joao M P Cardoso, Horacio C Neto*
University of Algarve/INESC, Portugal
*IST/INESC, Lisboa, Portugal
Object-Oriented Modeling and Co-Simulation of Embedded Electronic
Systems
Flavio Rech Wagner, Luigi Carro*, Marcio Oyamada, Marcio Kreutz
Universidade Federal do Rio Grande do Sul, Computer Science
Institute, Porto Alegre, Brazil
*Universidade Federal do Rio Grande do Sul, Electrical
Engineering Department, Porto Alegre, Brazil
Architectural synthesis dedicated to sub-micron technologies and
complex applications: an approach allowing interconnection cost
control
C. Jigo, E. Casseau, E. Martin
LESTER-UBS Laboratory, France
Special Sessions:
-----------------
S1 - Microsystems
CAE environment for electromechanical microsystems
R. Lerch, M. Kaltenbacher, H. Landes
Institute of Electrical Measurement Technology, University of Linz
Cost Consideration for Application Specific Microsystems' Physical
Design Stages: A new approach for microtechnological process
design
R. Brueck, A. Priebe, K. Hahn
Institut of Computer Structures, University of Siegen
Moving MEMS into Mainstream Applications : The MEMSCAP Solution
K. Liateni, D. Moulinier, B. Affour, A. Delpoux, J.M. Karam
MEMSCAP
S2 - RF Design and Analysis
Integrated Circuit Techniques for Wireless Transceivers
Mihai Banu
Bell Labs Lucent Tech
Trends in RF Simulation Algorithms
Joel Phillips
Cadence Research Labs
Device Modeling and Measurement for RF Systems
Franz Sischka
HP-EESof
S3 - Reconfigurable Hardware Systems
Reconfigurable Hardware Systems: Trends and Applications
Alexandro Adario, Sergio Bampi
UFRGS University, Brasil
Run-Time Reconfiguration: The State of the Art
Brad Hutchings
Brigham Young Univ. USA
ILP-Based Board-Level Routing of Multi-Terminal Network
Prototyping Reconfigurable Interconnect
Andreas Kirschbaum, Juergen Becker, Manfred Glesner
Technical Univ. Darmstadt, Germany
S4 - Architectural Synthesis and Verification
Hardware Synthesis from Term Rewriting Systems
James C. Hoe and Arvind
MIT Laboratory for Computer Science
A Synthesis Algorithm for Modular Design of Pipelined Circuits
Maria-Cristina Marinescu and Martin Rinard (30mn)
MIT Laboratory for Computer Science
S5 - Timing and Verification
Recent advances in high-speed low-power asynchronous circuits
Peter Beerel
University of Southern California, CA, USA
Solving design problems with static timing analysis
Tim Burks
Magma Design Automation, CA, USA
Retiming theory and practice
Marios Papaefthymiou
University of Michigan, MI, USA
Embedded Tutorials:
-------------------
E1 - CAD for Microelectromemchanical systems (2h)
Design of Integrated Systems including MEMS and ASICs
John R. Gilbert, Stephen F. Bart, and Bart F. Romanowicz
Microcosm Technologies
E2 - Interconnect Process Parametrization
SIPPs, why do we need a new standard for interconnect process
parameters?
Martin G. Walker, Keh-Jeng (KJ) Chang, Christophe J. Bianchi
Frequency Technology
E3 - Design of Video Systems on Chip
An interface based approach to the design of Video Systems on Chip
J.Y. Brunel and W. M. Kruijtzer
Philips Research Labs
-------------------------------------------------------------------------------
Wednesday, 1st of December
--------------------------
8:00am - Conference Registration
9:00am - 10:30am Opening Session
10:30am - 11:00am Coffee Break
11:00am - 12:30pm S2 Plenary
12:30pm - 2:00pm Lunch
2:00pm - 4:00pm V6 | C6
4:00pm - 6:00pm S1 | S4
6:30pm - 7:30pm Conference Reception
Thursday, 2nd of December
--------------------------
9:00am - 10:30am V1 | C1
10:30am - 11:00am Coffee Break
11:00am - 12:30pm V2 | C4
12:30pm - 2:00pm Lunch
2:00pm - 4:00pm E1 Plenary
4:00pm - 6:00pm S3 | E3
8:00pm - Conference Banquet
Friday, 3rd of December
--------------------------
9:00am - 10:30am V3 | C2
10:30am - 11:00am Coffee Break
11:00am - 12:30pm E2 | S5
12:30pm - 2:00pm Lunch
2:00pm - 4:00pm V5 | C5
4:00pm - 6:00pm V4 | C3
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