Re: [SI-LIST] : Physcially-small far-end LVDS terminations?

About this list Date view Thread view Subject view Author view

From: D. C. Sessions ([email protected])
Date: Tue Dec 21 1999 - 12:44:21 PST

Eric Goodill wrote:
> "D. C. Sessions" wrote:
> >
> > Keep in mind that common-mode potential almost^H^H^H^H^H^H always
> > affects input delay, so those reflections WILL show up as receiver
> > jitter. If your application is completely insensitive to jitter,
> > well and good. Offhand I can't think of any like that.
> D.C.,
> Could you please elaborate slightly about how common-mode affects
> differential timing on the inputs?

It's an operating-point thing. The transconductance of the input
devices isn't constant across the common-mode range. In addition,
thanks to LVDS' absurdly wide common-mode range, the PMOS input
stage goes into cutoff at the high end (2.4v against a 3.0v supply
just doesn't work) so there has to be an NMOS stage and some kind
of crossover mechanism to use the NMOS devices at high input voltage
and the PMOS one at low voltage. Not only do both the NMOS and
the PMOS vary in performance according to input common-mode point,
but they can't be matched perfectly and so the crossover introduces
even more variation.

Since the input delay varies with common-mode operating point, any
common-mode components will show up as receiver jitter.

D. C. Sessions
[email protected]

**** To unsubscribe from si-list: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at ****

About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:11 PST