From: Abe Riazi ([email protected])
Date: Wed Dec 01 1999 - 19:59:49 PST
Syed Huq Wrote:
>
>Then use a hdf and con file to define the hierarchy of boards connecting
>to each other and the 'mapping' of the connections(con file). This con file
>describes how the nets get tied across the connector.(See examples in Ch7 of
>'Preparing PCB database for simulation with TLC/XTK/QUIET').
>
>Then follow the translation process and it's a piece of cake.
>
>% tmp -hdf <design>.hdf
>% isf2xtk -hdf <design>.hdf
>
>Regards,
>Syed
>Cisco Systems, Inc
Hi Syed:
Let me add that when creating connection files careful attention
should be paid to the pin names of the mating connectors, in order to
determine if any swap files are required (which then needs to be
specified in the .con file). Furthermore, when carrying out multi-board
hierarchical simulation, it is advisable to create a Net file (,net) to
limit the system simulation only to those nets or buses of interest,
thereby enhancing the simulation efficiency. I have discovered that the
TMP program has some important limitations when executed in conjunction
with a Net file. However, ISF2XTK cooperates well with .net and
generates a Topology file containing only those nets dictated by the Net
file.
Best Regards,
Abe Raizi
Anigma, Inc.
**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list
****
This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:04 PST