From: Sandy Taylor ([email protected])
Date: Fri Nov 19 1999 - 15:27:21 PST
David Haedge wrote:
> I have an ASIC vendor that claims that *each* VDD bond pad on the die forms a
> capacitor of over 200pF, referenced to the VSS rail.
Using gate oxide for a decoupling capacitor in the region of the pad
in a generic 0.6u process you would have about 3.7fF/u**2.
So 200pF would be square 232u on a side. That could be done.
In a more modern process it would be easy.
The last microprocessor I worked on had well over 100 nF (total)
decoupling between VDD and VSS.
If your ASIC is in a technology below 0.6u, then I would believe 200pF.
This will help you mitigate the internal collapse of the power supply,
but if most pins switch in the same direction, you can still suffer
from the package inductive effects.
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