Johnson and Graham, in "High Speed Digital Design - A handbook of
Black Magic" discuss "Rents Rule" on page 216. Quoting:
Pavg = (((XY)^0.5)*2.7M)/N
where:
N is the number of connections,
Pavg is the average trace pitch in inches,
X is board width in inches,
Y is board height in inches, and
M is the number of routing layers.
The text points out limitations and disclaimers, etc. The point
being that this is an approximation which should be rounded up
to the nearest even number.
I hate giving endorsements, but a company called XYNETIX has a tool
which helps pre plan both placement and routing. I've seen the demo,
but have no user experience.
Best of luck,
Dennis
[email protected] wrote:
>
> Dear SI experts,
>
> Does somebody know how to estimate the total layers needed or trace's spacing
> and width based on the number of interconnection and
> ,surface mount device or DIP components, and board dimension?
>
> Thank you for helps in advance.
>
> John Lin
> CAE Engineer @ Arima Computer Corp.
>
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