Depending on your level of desired accuracy, the problem varies from simple to complex. If you have time :), on the academic side there have been two significant bodies of work in this area, one by Wemple and Yang, one by
Verghese and Allstot, both around the time frame of 1992-1995. Verghese's dissertation was also published in hardcover by Kluwer. However, to my knowledge, neither has been developed into an industry tool. The gist of each was
to model uniformly doped silicon as a resistive mesh, reverse-biased pn junctions as capacitive surfaces.
I do know that Avant! has developed a tool (Star-Crunch?) for reducing the large RC netlists resulting from either approach prior to simulation. Another company marketed a tool called "SI-Crunch" (spelling may vary) to perform
similar operations.
Hope this helps...
-- Steve
-------------------------------------------
Steven D. Corey, Ph.D.
Time Domain Analysis Systems, Inc.
"The Interconnect Modeling Company."
http://www.tdasystems.com
email: [email protected]
phone/fax: (206) 527-1849
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R.S.Krishnan wrote:
> Hi,
>
> I have a Clock chip design that has some Clock outputs on
> its VSS pin(s) and the rest of the outputs on a different VSS pin(s).
>
> On Silicon, we have observed that there exists interaction between
> these sets of outputs. The VDD of the outputs are separate too.
> The two sets of VSS pins are not connected on chip (except through
> the psubstrate). I would like to know how to model this substrate
> connection between the two VSS.
>
> Thanks
> Krishnan
>
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