[SI-LIST] : =?iso-8859-1?Q?=BB=D8=B8=B4:_=5BSI-LIST=5D_:_A_timing_question_in_hig?=

=?iso-8859-1?B?wfXK97Hy?= ([email protected])
Wed, 18 Nov 1998 09:58:55 +0800

My design is not a source synchronous clocking scheme. The clock souce mu=
be on one of the daughter boards and be driven to others and of course th=
clock on each daughter board should be synchronous . And the bus is to be=
share bus , the data both may be driven from the clock daughter board to =
others , and may be driven from the others to the clock board . So I thin=
k I
have to take the flight time into account.
Is the part not faster enough ? Why the NESA's paper "An Innovative
Distributed Termination Scheme for GTL Backplane Bus Designs" says that
their design use GTL+ (The author mentioned SN74GTL16622 in the reference=

-----Original Message-----
=B7=A2=BC=FE=C8=CB: Muranyi, Arpad <[email protected]>
=CA=D5=BC=FE=C8=CB: "A Signal Integrity Email list" <[email protected]=
n.COM>; "???"
<[email protected]>
=C8=D5=C6=DA: 1998=C4=EA11=D4=C218=C8=D5 0:39
=D6=F7=CC=E2: RE: [SI-LIST] : A timing question in high speed bus

Are you talking about a source synchronous clocking scheme when you say "=

design is to be a Synchronous clock one"? If so, the flight time falls o=
the equation and only the skews need to be worried about. (Source
means that both the data and the clock [strobe] are sent by the driver
device to
the receiver and they travel down the distance side by side. So it doesn=
matter how long it takes for the signal to get there as long as they get


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