ELECTRICAL MODELING,
SIMULATION, AND DESIGN OF
INTERCONNECTS
An Intensive Three-Day Short Course
San Jose, California
November 9-11, 1998
Offered by
Raj Mittra/Penn State, Paul Franzon /N. C. State, and Dale Becker/IBM
Poughkeepsie
UNDER THE SPONSORSHIP
OF
THE NORTHEAST CONSORTIUM FOR ENGINEERING EDUCATION (NCEE)
ELECTRICAL MODELING, SIMULATION, AND DESIGN OF INTERCONNECTS
COURSE DESCRIPTION
This three-day short course will provide an in-depth coverage of numerous=
aspects of electrical modeling, simulation and design with emphasis on
=91on-chip=94 interconnects.
Various design options will be discussed and the electrical issues in
interconnect design will be identified.=A0 Detailed design procedures wil=
l
be
outlined and the use of CAD/CAE tools for interconnect layout will be
described.
Techniques for electromagnetic modeling and simulation of interconnects,
multi-conductor transmission lines, and discontinuities in these lines,
e.g.,
crossovers, bends and vias, will be presented.
Methods for estimating the power and ground plane noise also will be
discussed.
LECTURERS
Dale Becker is a Senior Engineer in the System 390 Division of IBM in
Poughkeepsie, NY. He leads the MCM design team that integrates and
implements
the multiprocessor design for IBM=92s large server platforms. Dr. Becker=92=
s
current interests focus on the electrical design of the components that
comprise a high-frequency CMOS processor system. He specializes in the
application of electromagnetic numerical methods to the issues of signal
integrity and simultaneous switching noise in electronic packaging, the
measurement of these phenomenon, and the verification of the models.
Paul Franzon is a Professor in the Department of=A0=A0=A0=A0=A0 Electrica=
l and
Computer
Engineering at North Carolina State University. He has ten years of
experience
in electronic systems design and design methodology research and
development,
including working at AT&T Bell Laboratories, and as the founding member o=
f
a
communications company. Dr. Franzon=92s current research interests focus =
on
the
design sciences/methodology for high-speed packaging and interconnect, an=
d
also
for high-speed and low-power chip design.=A0 He is a consultant to a numb=
er
of
companies in these areas and has extensive experience in teaching related=
professional courses.
Raj Mittra is a Professor in the Department of Electrical Engineering at
the
Pennsylvania State University and Director of the Electromagnetic
Communication
Research Laboratory. He has directed many short courses on Electronic
Packaging
and Computational Electromagnetics, both in the U.S. and in Europe, and
has
offered on-site seminar series at several industrial locations including
GTE
Network Systems, Cray Research, DEC, IBM and Intel. He has authored and
co-authored over 480 research papers and 35 textbooks. He has served the
IEEE
AP-S Society as a National Distinguished Lecturer, as President, and as a=
n
Editor of the IEEE Transactions on Antennas and Propagation. He also head=
s
RM
Associates, a company that provides consulting services to many governmen=
t
and
industrial organizations.
COURSE OUTLINE
DESIGN INTRODUCTION
Introduction:
=A8 Overview of interconnect hierarchy
=A8 Signal integrity and synchronous design
UNDERSTANDING AND ANALYSIS OF ELECTRICAL INTERCONNECT STRUCTURES
=A8 Deciding on model fidelity.
Transmission line vs. other models, skin effect
=A8 Sources of noise and signal degradation and their control.
Reflection, crosstalk, SSN other common mode noise sources and control
Introduction to EMC
DESIGN OF ELECTRICAL INTERCONNECT STRUCTURES AND CIRCUITS, ELECTRICAL
DESIGN OF
PACKAGING, BOARDS, AND MCMS
=A8 Interconnect decision making.
Noise budgeting, eye diagrams.
=A8 Package decision making.
Criteria, techniques, CAD tools.
=A8 PCB layout and termination issues.
Noise budgeting, CAD tools.
=A8 Cable issues.
Modeling.
=A8 On-chip interconnect delay and noise issues.
Differences to package level. Design and extraction issues.
Signal Distribution Modeling and Simulation
=A8 Principles of signal integrity (SI)
=A8 Low-loss interconnects
=A8 Application to on-chip high-loss interconnects
=A8 Unique SI issues for on-chip interconnects
The role of inductance and wide buses at high-frequencies
=A8 Modeling and extraction issues
=A8 Model development and verification
=A8 The application of available extraction tools to existing design
=A8 Noise and timing budgets
Power Distribution Modeling and Simulation
=A8 Noise components
=A0=A0=A0=A0=A0=A0 Simultaneous switching noises (I/O); Core switching no=
ise;
Power transients; Frequency response and resonances
=A8 Modeling considerations
Partitioning for modeling and simulation tools; Modeling on-chip power
distribution; Predicting voltage and ground variations at the circuit
=A8 Decoupling strategy
Noise budgets and limits; Capacitor choice on-chip and off-chip; Capacito=
r
placement
=A8 Measurement and verification
System Design Considerations
=A8 Example of a ten processor 400 MHz system
Integrating a chip into a system environment; Budgets =BE Power, Noise,
Timing,
Clock Skew; Modeling tools; Verification and validation
Methods for Capacitance Computation of On-chip Interconnects
=A8 Electric field; electrostatic potential; Gauss=92s Law; Laplace=92s a=
nd
Poisson=92s
equations; capacitance of=A0 multi-conductor systems
=A8 Method of moments and the boundary element method; application to
capacitance
calculations for single and multiple lines; three-dimensional capacitance=
calculations
=A8 Introduction to finite element method (FEM); application to capacitan=
ce
and
inductance calculations for uniform and multiple lines with etches of
arbitrary
cross-section; extension to three-dimensional calculations of complex
geometries
=A8 Efficient Finite Difference Method for general-purpose of interconnec=
ts;
Capacitance Computation; Techniques for speeding up the computation of
large,
complex, interconnect structures
High Frequency Effects
=A8 Introduction to Finite Difference Time Domain (FDTD) algorithm; model=
ing
of
arbitrary structures including transmission lines, discontinuities, e.g.,=
bends, vias; extraction of equivalent circuits of discontinuities for
insertion
into SPICE and SPICE-type circuit simulation algorithms
Comparison and Code Descriptions
=A8 Comparison between various modeling approaches and recommendations as=
to
when
to use what
=A8 Brief descriptions of available computer codes
Power plane Noise Modeling
=A8 Electrical modeling of single and multilayer power planes
=A8 Computation of Leff and equivalent capacitance of power planes
=A8 Application to the estimation of delta-I noise
GENERAL INFORMATION
To register:=A0 Early registration is advised. Complete and return the
Registration Form or phone the registrar, Kelly Brown, at 407-892-6146, o=
r
FAX
407-892-0406, or e-mail at: [email protected]=A0 (note number 1 not lett=
er
el
before @). For technical information telephone Raj Mittra at 814-865-1298=
,
or
FAX 814-865-1299, or e-mail: [email protected] (note number 1 not lette=
r
el
after R); Paul Franzon at 919-515-7351, or e-mail: [email protected];
Dale
Becker at 914-435-6735, or=A0=A0=A0 e-mail:=A0 [email protected].
Attendance is limited. Register early to guarantee your course materials.=
Fee:=A0 The registration fee is $1,050.00 for the course. This fee includ=
es
all
course materials and refreshment breaks.
Schedule: Registration and check-in will be from 8:30 a.m.- 9:00 a.m. on
the
first day.=A0 The seminar hours will be 9:00 a.m. - 12:00 noon and 1:30 p=
=2Em.
-
4:30 p.m. each day.
Location: The course will be held at the Hyatt San Jose - Airport, 1740
North
First Street, San Jose, CA=A0 95112.=A0 The telephone number is 408-993-1=
234.
Lodging:=A0 If you need overnight accommodations, contact the Hyatt San J=
ose
-
Airport, 1740 North First Street, San Jose, CA=A0 95112, 408-271-3331. Be=
sure to
mention that you are attending the "Electrical Modeling, Simulation, and
Design
of Interconnects" course to receive the special conference rate.=A0 Reser=
ve
your
room before October 8, 1998, to be guaranteed the special conference rate=
=2E
Continuing Education Units: This program will be assigned 4 Continuing
Education
Units (CEU's). A certificate of course completion will be awarded.
Substitutions and Refunds:=A0 Substitutions may be made at any time. If f=
or
any
reason whatsoever you cannot attend, the entire tuition fee, minus $25.00=
administration fee, will be refunded if cancellation is received before
the
start date of the course, and no refunds will be made after that. Please
register early.
In-house program:=A0 This program is also available for on-site
presentations.=A0 If
you are interested in a tailor-made program to be offered at your company=
site,
please call Raj Mittra at 814-865-1298 for further information, or contac=
t
via
fax/e-mail.
Electrical Modeling, Simulation And Design Of Interconnects November 9-11=
,
1998
=95 San Jose, California
THE NORTHEAST CONSORTIUM FOR ENGINEERING EDUCATION (NCEE)
REGISTRATION FORM Attendance is limited. Please register early.
Last Name=A0 (Please Print)=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
First Name Middle Initial E-mail
Address((Please Print)
Institution/Organization Title/Position
Address
City State Zip + 4
Area Code Home Phone Area Code Business Phone Fax
Check appropriate item: Make checks payable to: Return this form to:
NCEE (Interconnects Course) NCEE
Central Florida Facility - Management Office
____=A0 $1,050.00 registration fee enclosed 1101 Massachusetts Avenue
St. Cloud, FL=A0 34769
____=A0 Bill me/my organization
(Billing authorization enclosed) Attention: Registrar's Office; Kelly
Brown,
Registrar
____=A0 Purchase order enclosed Phone:=A0 407-892-6146;=A0 FAX:=A0 407-89=
2-0406
NCEE Central Florida Facility1101 Massachusetts AvenueSt. Cloud, FL=A0 34=
769
-- =
Paul Franzon, Professor, North Carolina State University
919 515 7351, fax. 919 515 2285, www.ece.ncsu.edu/erl/faculty/paulf.html
Rm. 443, Engineering Graduate Research Center, Centennial Campus
smail: ECE, Box 7914, NCSU, Raleigh NC 27695-7914
Fedex: Rm. 419, EGRC, 1010 Main Campus Dve, NCSU, Raleigh NC 27695-7914
--PART-BOUNDARY=.19809291142.ZM23734.ncsu.edu--
**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****