Re: [SI-LIST] : Conducted EMC Testing of PLL jitter

[email protected]
Tue, 29 Sep 1998 16:22:49 EDT


For direct driving of the board, time delays (because of propagation speeds)
and resonances will be encountered at the higher frequencies which may be a
desireable thing if your layout is already fixed. Your selection as to where
you place your driving source will affect these resonances and the expected
interactions as well. You may want to inject the ripple at various locations
around the board to check for consistency of response.

A possible downside of your noted approach is that OTHER circuts may react to
the planar noise; hence, you may not be able to separate the PLL circuit
susceptibiliity to noise.

To isolate the PLL susceptibility, I suggest you consider lifting the PLL
power pin, inserting a small resistor (perhaps 100 milliohms) in series, and
differentially driving the resistor via a transformer as you had planned. I
suspect (for current chip designs) that only the higher frequencies (i.e., 100
kHz and up) will have any affect; hence, a ferrite-based transformer should be

Good Engineering to you,

Mike Conn
Owner/Principal Consultant
Mikon Consulting