Re: [SI-LIST] : Conducted EMC Testing of PLL jitter

Pat Zabinski ([email protected])
Tue, 29 Sep 1998 13:14:20 -0500


Without much more detail on your board, it's difficult to tell, but
I believe over the DC to 1 GHz frequency range the board will
have several resonances. That being the case, the impedance
of the board will be far from constant.

On a test board that we ran (2x3x0.062 inches of FR4), the impedance
of the board when measured from a corner varied from milliohms
to a few hundred ohms! The impedance was also very dependent upon
location of the probe point.

Based on this experience, I would tend to believe any form of
impedance matching would either be useless or very difficult.

If your amplifier can handle a direct short on its output, I suggest
connecting it directly the planes without any impedance matching.

As an alternative, we have used simple FETs to short out the planes.
Essentially, we connect the drain and source to VDD and VSS, respectively,
then connect a signal generator (square or sinusoidal wave) between
the gate and source. Doing it this way, you can more easily match
the impeadances. By selecting the proper FET, you can effectively
short the planes over a broad frequency range, thus providing 'noise'.
The noise injected by this method will be based on current surges (vs
the voltage injection you proposed), but I believe it is more
controllable and representative of the real world.

Hope this helps,

On Sep 29, 9:51am, Ray Anderson wrote:
> Subject: [SI-LIST] : Conducted EMC Testing of PLL jitter
> Perhaps some of the EMI/EMC savvy people on the list have
> some comments and/or opinions on how best to couple an interfering
> RF signal into the power planes of a digital board to accomplish
> some EMC testing.
> Basically I have a system (CPU's, memory, PLL's etc.) that
> runs at a clock rate of several hundred MHz. I need to do
> some tests to evaluate what effect noise on the power planes
> over the range of ~DC to 1GHz has on the PLL jitter.
> I would like to inject a signal (in the range of ~DC to 1 GHz)
> into the power planes (up to maybe 200 mv p-p amplitude) to
> see how the PLL handles the noise on it's power feed.
> I have a broadband (10KHz to 1GHz) amplifier that can provide
> an excitation level of up to 20 watts into 50 ohms.
> We believe the system power distribution system (planes, bypass
> caps etc.) looks like a broadband 50 milliohm (or less) impedance.
> The question is: would impedance matching the 50 ohm amplifier
> impedance to the sub-ohm plane impedance by means of a broadband
> ferrite transmission line transformer be a prudent thing to do,
> or is there another accepted way of doing this?
> Any comments or suggestions on alternate ways of evaluating the
> jitter performance of a system PLL in response to power supply
> noise over a wide bandwidth would be of interest.
> Ray Anderson
> Sun Microsystems Inc.
> [email protected]
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