FWD+: Re: [SI-LIST] : Trace impedance

Dr. Edward P. Sayre ([email protected])
Wed, 26 Aug 1998 18:46:24 -0400

I concur completly with Bob Haller. The secret is being careful and using
measurement equipment with sufficient bandwidth.

For PCB design, getting accurate cross-section information is often
difficult. We at NESA try to pre-position ourselves with PCB vendors who
we know from past experience either follow the construction we specify or
know how to achieve predictable impedance results from their past
experience. Ask to see the impedance data base results before you commit
to an important fabrication.

Comparing measured to simulated results is often a matter of "eyeballing"
the results because importing measured results into SPICE can be difficult.
When all else fails, output the SPICE and measured results to .TXT or other
suitable deliniated files, hand edit them to import them into Excel and
overlay the data sets.

ed sayre
--------------------------------------------
>From: [email protected]
>Date: Wed, 26 Aug 98 17:00:26 EDT
>To: [email protected]
>Cc: [email protected]
>Apparently-To: [email protected]
>Subject: FWD+: Re: [SI-LIST] : Trace impedance
>Sender: [email protected]
>
>I agree with Fabrizio. Get a good field solver. I have found that if I use
our
>internal field solver I can accurately predict impedance, delay and
crosstalk.
>Moreover if I feed the results into HSPICE (using wline models) I can get
near
>perfect match when I overlaying bench waveforms and HSPICE simulated
waveforms.
>I recommend;
>
>1. Measure impedance, delay, and response to some input stimulus using a
> high bandwidth scope and TDR.
>2. Accurately measure actual physical geometries of traces from
cross-sections.
>3. Create spice model (or RLGC file) from field solver (if possible).
>4. Compare Measured results to simulated results
>
>One can obtain excellent correlation, as good as test equipment measurement
>accuracy provided your have a 'good' field solver and accurate input
>information. just my $.02.
>regards, bob
>
> Robert J. Haller
> Principal Hardware Engineer
> Compaq Computer Corporation (formerly Digital)
> 129 Parker St. PK03-01/N97
> Maynard Ma. 01754-32198
>
> (978) 493-4112
> [email protected]
>
>
>-----------------Forwarded item dated 20-AUG-1998
13:49:10.16-----------------
>
>From: US8RMC::"fabrizio=zanella%eng%[email protected]"
>To: "casperdd" <[email protected]>, <[email protected]>
>CC: "[email protected]" <[email protected]>
>Subj: Re: [SI-LIST] : Trace impedance
>
>Gentlemen, formulae for calculating impedances of stripline/microstrip
>traces are only somewhat accurate for certain geometries. The formulae
>were developed many years ago, when line widths were .010"+, dielectric
>thicknesses differed from today's designs, and most designs used 50 ohm
>transmission lines. For high impedance tlines, (80+ ohms), the accuracy of
>the formulae gets terrible.
>If you want to match your TDR measured impedances to calculations, you need
>to use a field solver tool. There are many good tools available that use
>boundary element or finite element analysis. Try Apsim's 'RLGC' tool, or
>Ansoft's Maxwell EZ2D.
>
>Regards,
>Fabrizio Zanella
>EMC Corporation
>[email protected]
>-------------
>Original Text
>From: "Bill Dempsey" <[email protected]>, on 8/20/98 1:05 PM:
>To: smtp@Eng@EMCHOP1["casperdd" <[email protected]>]
>Cc: smtp@Eng@EMCHOP1["[email protected]"
><[email protected]>]
>
>casperdd wrote:
>
>> Hi
>>
>> I was hoping that someone might be able to shed a little light on a
>> problem that I have encountered regarding the impedance of stripline,
>> and microstrip PCB tracks.
>> I require a formula that is capable of predicting the impedance's of
>> stripline, and microstrip tracks. I have already found several from
>> different source, but none of them seem to agree with each other, my
>> TDR
>> results, or the TDR results from "MECL system design handbook" by
>> Motorola. All the formulas that I have come across claim to have an
>> accuracy to within about 5%, but as far as I can tell the discrepancy
>> can reach up to 20%, depending on the dimensions involved.
>> The region of interest to me is:
>>
>> Track width = 10 mils
>> Track thickness = 1.37 mils
>> Ground plane/Track separation (dielectric height) = 8 mils
>> Relative permittivity = 4.7
>> TDR edge rise time = 28ps
>>
>> The most alarming problem that I have encountered is the natural
>> logarithm that most formula seem to have, this then returns a negative
>>
>> number when its argument is smaller than one, even though most formula
>>
>> claim to still be accurate at this limit.
>>
>> I would appreciate it if anyone could show me where I have been going
>> wrong, or point me in the direction of an accurate formula.
>
>Plenty of research has gone into most of the formulas. Assuming a
>"fixed" value of er= 4.7 somewhat troubles me as this value is not a
>constant over frequency. er = 4.7 *seems* high to me. I suspect you'll
>be able to empirically determine the er at the frequency of interest if
>you build some test boards. Most good board shops know how their
>material acts at these higher frequencies and back their numbers up with
>real-world measurements. Check around and see what they think your
>materials' er is in the gigahertz region.
>
>Also check with IPC -- they have a technical paper IPC-TP-949 that
>covers measuring impedance of stripline/microstrip traces. It's written
>for the layman so it's easy to read.
>
>Hope this helps,
>Bill Dempsey
>
>
>
>>
>>
>> Many Thanks
>>
>> Dominic Casperson
>>
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+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
| NORTH EAST SYSTEMS ASSOCIATES, INC. |
| ------------------------------------- |
| "High Performance Engineering & Design" |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
| Dr. Ed Sayre e-mail: [email protected] |
| NESA, Inc. http://www.nesa.com/ |
| 636 Great Road Tel +1.978.897-8787 |
| Stow, MA 01775 USA Fax +1.978.897-5359 |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+

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