I would like to add two general comments to the good ones already presented
by Ray Anderson and Larry Smith
1. The self inductance of the capacitor also depends on the internal
construction of the capacitor and the location of the terminals. For
example if one terminates the capacitor on the wide side of the rectangular
package instead of the narrow side, the inductance is decreased; thus one
might choose a 0612 capacitor instead of a 1206. They are physically the
same size but have terminations on different faces. For another example,
see the 'LICA' capacitors from AVX which have dramatically lower inductance
and larger self-resonant frequencies than the standard surface mount caps
with terminations on each end.
2. If one wants to accurately know the high frequency behavior of a mounted
capacitor, it is necessary to include all of the nearby environment (other
traces, ground and power planes, etc) specific to each situation. When one
is dealing with very small parasitic elements, small changes in the
environment can be surprisingly significant. In particular, for any
contribution to the inductance as discussed here, it is possible and often
desirable to compensate that inductance either partially or totally by
careful layout and component placement. In my opinion, this is best done
by developing generic design rules for each particular stack-up using a
suitable modeling tool (like Ansoft's Quick 3D Extractor) and then applying
those rules where needed.
The bottom line is that with the right tools designers can compensate for
the inductance of vias, pads, capacitors, etc just like the manufacturerers
do. Then the capacitor specs are meaningful and one can pick a suitable
capacitor and use it to its full capability.
Best regards,
Eric
-----------------------------------------------------------------
Eric Wheatley Ph.D. Electromagnetic Modeling Services
Alterra Technology Co. (760) 942-9426 (phone)
435 Dunsmore Ct. (760) 942-2366 (fax)
Encinitas, CA 92024 US [email protected]
-----------------------------------------------------------------
At 10:07 AM 8/11/98 -0700, you wrote:
>Tanmoy Roy, John Prymack and myself will be presenting a paper
>in October at the EPEP conference that goes into a little more
>depth on the mounted inductance of decoupling capacitors. We
>find that there are 3 major contributers capacitor inductance:
>
> pad and via design 1.00 to 4.00 nH
> plane spreading inductance 0.01 to 0.50 nH
> capacitor height 0.20 to 0.40 nH
>
>The three components sum together. Inductance is essentially a
>measurement of the flux or B field in the environment caused by
>current going around a loop. The bigger the loop, the more the
>flux and the more the inducance.
>
>As Ray stated below, the pad and via design are the most important
>contributers to capacitor inductance. The design of the power planes
>(PCB stackup) is second in importance. Third in importance is the
>capacitor height. If the capacitor manufacturer has compensated out
>the first two contributors to inductance (given you the self
>inductance of the capacitor) the third (and least important) part is
>all you get. Inductance numbers quoted for surface mount devices
>are often mis-interpreted or mis-understood.
>
>Come to the EPEP in West Point NY on October 26-28 and get the
>rest of the story!
>
>regards,
>Larry Smith
>Sun Microsystems
>
>
>> Date: Tue, 11 Aug 1998 09:17:13 -0700 (PDT)
>> From: Ray Anderson <[email protected]>
>> Subject: Re: [SI-LIST] : Surface Mount Cap Lead Inductance
>> To: [email protected]
>> Cc: [email protected]
>> Mime-Version: 1.0
>>
>>
>> You will probably find that the ESL of the capacitor
>> is only a small part of the "mounted inductance" of the part
>> when it is placed on a PCB. A larger percentage of the total
>> loop inductance that your circuit sees associated with a mounted
>> capacitor comes from the following factors:
>>
>> 1 Pad Geometry
>> connector traces
>> via location
>> Number of vias
>>
>> 2 Stackup
>> distance from mounting pads to power planes
>>
>> All those factors that influence the loop area seen by the current
>> flowing through the capacitor influence the mounted inductance. The amount
>> contributed by the capacitor is a small part and is usually overwhelmed by
>> the other constituents unless you do a VERY good job in minimizing the
other
>> contributions (which can be done). The ESL of the capacitor by itself is a
>> very strong function of the height dimension of the part.
>>
>> It is the mounted inductance of a bypass capacitor that mostly
>determines
>> the effectivness of the bypassing that the part provides.
>>
>>
>> Ray Anderson
>>
>> Sun Microsystems Inc.
>>
>> > From: Vigliarolo Roberto <[email protected]>
>> > To: [email protected]
>> > Subject: Re: [SI-LIST] : Surface Mount Cap Lead Inductance
>> > Date: Tue, 11 Aug 1998 17:55:15 +0200
>> > X-Priority: 3
>> > MIME-Version: 1.0
>> > Content-Transfer-Encoding: quoted-printable
>> >
>> > You can easily calculate the ESL of your capacitor by looking at the
>> > frequency of the dip in the impedance vs frequency chart usually
>> > provided by capacitors manufacturer. Fresonance=1/(2*pi*sqrt(ESL*C))