I think this design problem can be broken up into several smaller steps.
Simplify your mainline (mainline is defined as the path from the two points
farthest apart in time on the net) plus stub topology into a single approximate
transmission line segment. Determine the total inductance in the mainline, and
the total capacitance in the mainline plus the stubs and the stub chips. Using
this total L and C calculate an approximate Z0 and time-of-flight for the
mainline.
Validate your approximation by controlling the relationship between the
round-trip time on each stub and the edge-rate of the signals on the bus. You
want your edge-rate to be slow enough that your stubs appear as lumped loads to
the signal, rather than transmission line stubs. This step is key. With stubs
the best you can achieve is a multi-reflection net with lots of ugly slope
reversals, plateaus and ringbacks. You may be able to play with series
terminations and parallel terminations to meet your timing goals, but if you
have a goal that includes single-reflection or incident characteristics you are
out of luck with electrically long stubs. Secondly, it is likely that choosing
a faster edge rate driver will not significantly speed up the overall timing of
the net. A driver with a faster unloaded delay is more appropriate for speeding
up the net. In extreme cases, I have used fast, low R drivers ganged in
parallel and a series RC filter to get the combined characteristics I wished.
Choose your driver output resistance (real driver Rout + close series damping
resistor) to match 1/2 the approximate Z of the mainline, because you will be
driving your mainline from the middle in some situations. If you can't specify
a driver with a low enough Rout, you will be back into a multi-reflection
regime, although a cleaner one because your edge rate will be slower than the
stubs.
Parallel termination gets added to nets like these to satisfy incident
switching requirements because it controls the reflections off the ends of the
mainline. It also appears on these kinds of nets because it is used to provide
the up-level drive, open-collector kinds of schemes work well because it is
hard to build low C, low Rout pullup devices.
With these kinds of approximations you can do your rough design and timings
with bounce diagrams. Check timing to the chip nearest the driving chip
(sometimes the driving chip listens to itself) under the heaviest loading
conditions, with the driving chip farthest from the ends of the mainline. Check
ringing conditions under the lightest loading conditions with the driving chip
at the end of the mainline, and the ringing victim at the other end of the
mainline. Check also where the driving chip is at the middle of the mainline
and one side is fully loaded, and the other side is minimally loaded. This can
invoke some interesting ringbacks.
Good Luck.
Joe
CEC Analysis and I/O Design
Phone: 507.253.0762 Fax: 507.253.4966
[email protected]
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