Re: [SI-LIST] : Decoupling:routing

larry smith ([email protected])
Thu, 30 Apr 1998 12:06:36 -0700 (PDT)

> Date: Thu, 30 Apr 1998 09:14:07 -0500 (CDT)
> From: [email protected] (Tom Zimmerman)
> Subject: Re: [SI-LIST] : Decoupling:routing
> To: [email protected]
> I think that the tradeoff here is that you introduce a bit longer effective
> lead length or inductance in the digital supply to obtain the benefit of ..
> cleaner ground. I don't have much experience with other types of systems,
> but I suspect that on systems where the ground referencing isn't quite so
> critical, you might want to minimize the lead length and therefore the supply
> bounce, at the expense of currents running through the ground plane. (???)
> That is, if you can tolerate some level of voltage differences across the
> plane. Where 1 mV would be a disaster for us, it could be insignificant for
> others. I'd be very interested in hearing any comments on this from
> designers of other systems. How much do people worry about this kind of
> thing?

Tom - you have a rather unique application, so the general rules I use
on high wattage micro processors and ASICs may not apply. My comment is
that the inductance of the trace used to hook up the decoupling capacitor
will resonate with other capacitors in the system. If chip Vdd is routed
to the capacitor (rather than via'd directly to the Vdd plane) the parasitic
decoupling capacitance on-chip will resonate with the trace inductance
at some frequency. Then, if a trace is used to hook the decoupling capacitor
to the Vdd plane, it will resonate with the decap. More inductance will
result in a higer "Q" circuit, meaning that it will really like to ring
at it's resonant frequency. On uP and ASICs with a lot of energy at
high frequency, it is best to minimize inductance by placing vias directly
to planes right under the chip and the decap. In your application, you
may be able to tolerate this high Q resonant circuit associated with
trace inductance, just be aware that at some frequency, it exists.

> I also wanted to comment on the other important issue for us: substrate
> coupling. We found out that for an IC built on an epi process (low
> resistivity substrate), the inductance between the substrate (back plane) and
> the system ground is a critical parameter. Great article about this in
> IEEE JSS, March 96 by Gharpurey and Meyer. This inductance is a common
> impedance between digital and analog sections on the same chip. Lucky for
> us, our application is very atypical and in fact requires that our chip NOT
> be packaged, but mounted as a bare die directly to the board (space and
> mass constraints inside the detector). This couldn't be better for minimizing
> substrate coupling. We lap and backplate the wafers so that the chips can
> be glued (conductively) directly to the ground plane/die pad on the board.
> Then the substrate to system ground inductance is VERY low. This works
> really well and virtually eliminates substrate coupling! In fact, we also
> use the substrate to conduct all the analog ground current. There are no
> AGND pads on the chip; all analog circuits are referenced through the
> backplane RIGHT to the system ground. The chip substrate is effectively
> just an extension of the system ground plane. DGND is NOT referenced through
> the substrate, but brought out to a pad, of course, for the reasons discussed
> before. Has anybody else had this experience or used this technique?

About 10 years ago, I worked on a similar project at IBM. We were building
a 64 bit flash a/d converter on a noisy logic chip. We had a low resistivity
substrate, similar to yours. We polished the backside of the wafer and
metalized it with a stackup that could actually be soldered down to a
conducting surface, which was at system ground. The low inductance
(impedance) chip substrate connection to system ground greatly reduced
the noise transfered from the logic to analog portions of our chip. We
concluded at that time that the only way to make this configuration
successful was to eliminate the electronic package and mount the chip
backside directly to a ground plane on the system board. It was not
practical for us at that time, but in low quantities and today's technolgy,
I think you can probably do it. Our solution was to go to a high resistivity
silicon substrate and attempt to isolate the analog and logic portions
of the chip by high resistance.

> A colleague of mine is building a fairly large PC board for another project
> and we have been discussing these issues. His board has a big all-digital
> section, and then a smaller analog section. The analog chips each have one
> digital output (a comparator output) which runs over to the digital section.
> He has board layers which are devoted exclusively to power and to ground.
> He's trying to bypass all the digital chips with the chip-cap-plane method,
> but it's a lot of work to do it that way, and he's not sure it's worth it.
> His situation is different than mine, and I'm not sure how to advise
> him. Have other people done this, and what are your experiences? His
> other question is whether to separate the ground planes for the digital and
> analog sections or not, and if so, do you reference them together at just
> one point? I tend to think there should be one common plane, but that's
> because of the experience I had, which may be quite different on a large
> mixed signal board with lots of parts.??

A continuous ground plane is best, common to both analog and digital
circuitry. If you attempt to isolate analog and digital ground planes,
a signal (output of comparator) that traverses the boundary will see
a huge inductive discontinuity. The rise time and therefor timing on
that signal will be poor. If several similar signals cross the same
boundary, you will create a simultaneous switch problem when all of
the signals attempt to switch the same direction at the same time. If
you put enough bypass capacitors across the power boundary to eliminate
the problem, then you might as well have had a continuous ground plane
to begin with. Continuous ground plane is the best solution.

Larry Smith
Sun Microsystems