Good question. There are cases SSO lead to negative "delay" with respect to
a reference level. But that will usually cost a "bounce back" to the other
polarity, and triggering another problem. One PLD company had a fast 3ns
part, but sold it as 5ns part, due to the reason of the return bounce took
another 1-1.5ns to settle. As a result, that company lost a huge business to
another competitor, when the other company clean up its SSO with big effort.
The AGP Design Guide over simplified the signal integrity issue. But as a
"guide", it did its job as a "guide" for new comer, but not to mis-guide(?)
good senior designers.
FYI
/frank
Chip & Chip
[email protected]
-----Original Message-----
From: Andrew Ingraham <[email protected]>
To: 'si-list' <[email protected]>
Date: Thursday, April 30, 1998 8:05 AM
Subject: [SI-LIST] : Does SSO make outputs earlier as well as later?
>We all know that simultaneous switching (SSO, or ground bounce) can add
>delay.
>
>But can it add negative delay, making outputs appear earlier than they
>would have without the SSO?
>
>I have always thought so ... based on the model that much of the effect
>is a simple addition of coupled noise into other outputs, which may
>appear to move their driven edges in either direction ... depending on
>whether all outputs switch in the same direction, or some go the other
>way.
>
>Reason for asking: the AGP Specification and Design Guide state that SSO
>can only add positive delay. See AGP ECR# 40
>(ftp://download.intel.com/pc-supp/platform/ecr40.pdf), which says: "SSO
>pushout only increases the delay of a buffer, never decreases it;" and:
>"While, all other skews are equally likely to reduce setup or hold time,
>SSO is different in that it only causes data delay and it cannot cause
>the signal to occur earlier." Aren't they wrong?
>
>Regards,
>Andy Ingraham
>