Re: [SI-LIST] : Decoupling:routing

Ravinder Ajmani ([email protected])
Mon, 27 Apr 1998 11:50:57 -0400

According to Dr. Howard Johnson, author of the book High-Speed Digital =
this is the preferred method of decoupling capacitors placement for hig=
boards. At high frequencies, even the small trace between capacitor an=
d the
power pin of the IC can have large impedance. For best results, the ca=
pads should be enlarged and vias placed within the pads. Otherwise, th=
e vias
should be placed as close to the pads as possible and connected through=
a fat

Ravinder Ajmani
Always do right. This will gratify some people and astonish the rest. =
Mark Twain

[email protected] on 04/27/98 08:34:02 AM
Please respond to [email protected]
To: [email protected]
Subject: [SI-LIST] : Decoupling:routing

I have been looking at several PWB designs and have noticed that t=
decoupling capacitors are placed near the power pins of the IC's.
However, the caps are not routed directly to the power pins. The
decoupling caps have a via connection to the power plane or ground=


Is there anything wrong with this?

My assumption is that the caps are placed near the component and a=
then routed directly to the power pins of the component on the top=


David Fontanez
[email protected]