[snip]
> The idea is first to get the impedance of all layers quite close, and
> secondly to get as much of the return currents as possible in the ground
> planes rather than the power planes (this is obviously not the case for
> signal layers 3 and 4, but I can keep my critical signals off them.
>
> Can anyone think of a better stackup, or are my priorities mixed up for a
> high speed (~100 MHz) digital board? Am I sacrificing high speed
> decoupling by not putting power and ground planes right next to each other?
> (One plane is 5V and the other is 3.3V, BTW)
The thing is, return currents *will* run in the power plane of the
driving device. Loops, Kirchoff, all that. If you force them to
go through the power-ground capacitance as well, you'll have
different impedances for rising and falling edges and lots more
induced noise.
In addition, your proposed stackup has a large gap between power
and ground, so this crossover between planes is going to be a
high impedance one as well.
Ideally, 5v signals would run between a 5v plane and a ground
plane, 3v signals would run between a 3v plane and a ground
plane, and power and ground planes would be paired. That would
give something like:
signal
GROUND
+3.3
signal
signal
GROUND
+5v
signal
signal
GROUND
+3.3
signal
but that's two more layers than you have, and assigns equal
numbers of layers to 5v and 3.3v signalling even though you
probably have much more (and more critical) at 3v than at
5v. If the 5v signalling is *reallY* localized I'd just
split the bottom 3v plane:
breakout
GROUND
3v signal
3v signal
+3.3
GROUND
3/5 signal
3/5 signal
+3.3/+5
breakout
This gets lower decoupling on the 5v section, but given
the greater high-side immunity of 5v signals that might
be tolerable. 3v integrity is pretty good, if not as
good as it would be with the planes paired. That's
life, since you can't pair evenly in a 10-layer stack.
-- D. C. Sessions [email protected]