The buried capacitance material to which John referred is a 2 mil thick
single-ply laminate. The use of this technology has certain costs
associated with it from a board fab standpoint. Roland may be referring
to having two cores separated by a single ply of b-stage (prepreg) as
pictured below. Either option implies that single-ply construction of
the board will be necessary. Most board shops are familiar with
single-ply constructions and use them wherever possible as a method of
cost reduction. If the scenario outlined below is used, the biggest
potential problem for a prepreg dielectric that is 2-2.5 mils thick is
the possibility of cut-through. This is where the two pieces of copper
facing each other on different cores form a shear and, when laminated,
cut through the glass reinforcement to become extremely close together
in the final board (this is not desirable). The chance of the
occurrence of this effect is minimized since the two pieces of copper
are wide planes and not isolated circuits (higher pressure zones).
Signal
xxxxxcore
Ground
prepreg
Power
xxxxxcore
Signal
Steve Silbert
[email protected]
-----Original Message-----
From: John Fisher [SMTP:[email protected]]
Sent: Tuesday, April 14, 1998 9:25 PM
To: Roland F. Portman
Cc: [email protected]
Subject: Re: [SI-LIST] : stackup question
Roland,
I thought that the standard core thicknesses at the thin end
were .002 and
.004 " .
Your fab house must be using a .002 single ply core plus some
prepreg.
This thickness is close to what the buried capacitance vendors
use.
Are your fab houses comfortable with this?
Any issues using the single ply laminates?
Regards,
John
*********************************************************************
John M. Fisher -- Cisco Systems -- [email protected]
170 W. Tasman Dr., Bldg G, San Jose CA 95134-1706
__ _ _
________/// \_/ \________/ \ ____
\/
Signal Integrity Engineer, Enterprise Line of Business
408-527-9186, Fax 408-526-5504, N6PFN
*********************************************************************
At 05:38 PM 4/14/98 -0700, you wrote:
>Paul,
>
>I have a simalar stackup for my 10 layer board. Only
difference is the
>location of Power 2 and Ground 2 .
>
>Put the most heavily used, high frequency, etc. power plane
pair in the
>middle of the board. Separate this
>pair by 2.5 mils of FR4. The results will be capacitive
coupling of
>these two planes (500 to 1000 pf/ sq. inch). This should help
very high
>frequency return currents. This doesn't mean you can remove
the 0.1uf
>0603 bypass caps that you have scattered around the board. I
haven't
>had much success removing bypass caps.
>Make up the board thickness by adding between Signals 2/3 and
signals
>4/5.
>
>Be sure BOTH grounds are electrically the same (tied together)
(each
>ground via attaches to both).
>
>That leaves a Ground at layer 2 and Power at layer 9. (See
Below)
>
>Be sure to make Signal 1, 2, 3, 4, 5, 6 nearly the same
impedance. Be
>sure to separate the
>traces on Signal 1 and Signal 2 a little more to reduce
crosstalk.
>Remember, crosstalk drops off
>by the square of the distance between the traces, so you don't
have to
>separate them too much more
>to gain significant results. Then concentrate your routing
>on the top side to signal 1 and 2, and on the bottom to signal
5 and
>6. This will help make sure the
>return currents go to the same return plane when you switch
layers.
>(We are trying to eliminate
>signal 3 and 4 and go for a 8 layer board, keeping the rest of
the
>stackup the same.)
>
>I hope this helps.
>
>Roland
>
>
>
>Paul Thompson wrote:
>>
>> I'd like to know what people think about the following
stackup for a 10
>> layer board with 2 power planes and 2 ground planes:
>
>
>> Signal 1
>> -4 mil-
>
>Ground
>
>> -5 mil-
>> Signal 2
>> -8 mil-
>> Signal 3
>> -5 mil-
>
>Power 1
>-2.5 mil-
>Ground
>
>> -5 mil-
>> Signal 4
>> -8 mil-
>> Signal 5
>> -5 mil-
>
>Power 2
>
>> -4 mil-
>> Signal 6
>>
>> The idea is first to get the impedance of all layers quite
close, and
>> secondly to get as much of the return currents as possible in
the ground
>> planes rather than the power planes (this is obviously not
the case for
>> signal layers 3 and 4, but I can keep my critical signals off
them.
>>
>> Can anyone think of a better stackup, or are my priorities
mixed up for a
>> high speed (~100 MHz) digital board? Am I sacrificing high
speed
>> decoupling by not putting power and ground planes right next
to each other?
>> (One plane is 5V and the other is 3.3V, BTW)
>>
>> Regards,
>>
>> Paul
>>
>> --
>> Paul Thompson
[email protected]
>> System Integrator, Macintosh Desktop Systems Apple
Computer
>
>Signal 1
>-4 mil-
>Ground 1
>-5 mil-
>Signal 2
>-8 mil-
>Signal 3
>-5 mil-
>Power 1
>-6 mil-
>Power 2
>-5 mil-
>Signal 4
>-8 mil-
>Signal 5
>-5 mil-
>Ground 2
>-4 mil-
>Signal 6
>
>The idea is first to get the impedance of all layers quite
close, and
>secondly to get as much of the return currents as possible in
the ground
>planes rather than the power planes (this is obviously not the
case for
>signal layers 3 and 4, but I can keep my critical signals off
them.
>
>Can anyone think of a better stackup, or are my priorities
mixed up for
>a
>high speed (~100 MHz) digital board? Am I sacrificing high
speed
>decoupling by not putting power and ground planes right next to
each
>other?
>(One plane is 5V and the other is 3.3V, BTW)
>
>Regards,
>
>Paul
>
>--
>Paul Thompson
[email protected]
>System Integrator, Macintosh Desktop Systems Apple
Computer
>
>