I'm playing with an ASIC that appears to put out the odd 10 ns "blip". The
rest of the circuit runs very low speed, say around 100 kHz to 2 MHz, except
for uP ALE and W/R, and appears to ignore this event.
The problem I have is controlling the radiated emissions that this blip gives
me on traces that leave the CPU board: filtering 30 to 40 lines is not
practical.
The power pins to the ASIC have some noise on them as you would expect, I
don't seem to correlate noise on the supply to the "blip", any thoughts on why
the ASIC would do this? Can I isolate parts of the ASIC by not applying power
to some of the 4 +Ve supply pins?
The ASIC is a copy of the FPGA I used in development, that part appeared to do
better but cost very much more...
Thanks,
Derek Walton
Owner L F Research EMC Design and Test Facility