I think you're right on in theory, although I've never examined the size
of the differences between SSO noise effects simulated in SPICE vs.
behavioral. Senthinathan and Prince do a great job of elucidating the
SSO negative feedback mechanism in their book, "Simultaneous Switching
Noise of CMOS Devices and Systems," section 3.2. To summarize, the more
the rails collapse because of di/dt noise, the lower the drive
capability of the output FETs, and the lower the di/dt - which reduces
the rail collapse. Rail collapse is much less than what you would
expect if you used the first-order approximation dV = N*Leff*di/dt.
(Thank God.) To my knowledge, an IBIS data sheet has no place-holder
for the parameters that play a part in this feedback mechanism.
At Digital, we use SPICE and fully-coupled package models to analyze SSO
noise. Someone else may use another method based on different accuracy
requirements.
Greg
----------
Greg Edlund, Principal Engineer
Server Product Development
Digital Equipment Corp.
129 Parker St. PKO3-1/20C
Maynard, MA 01754
(978) 493-4157 voice
(978) 493-0941 FAX
[email protected]
----------
From: Brian Young[SMTP:[email protected]]
Sent: Thursday, April 02, 1998 8:50 AM
To: [email protected]
Subject: Re: [SI-LIST] : Output Impedance
I'm convinced IBIS works great if you have no rail collapse so
that the IV
curves are valid. I don't think they are valid under heavy bus
switching
with significant rail collapse, although I hear people claim
otherwise. I
just don't see how IV curves provided at, say 3.3V, work when
you have 0.5V
of collapse. Any comments?
Brian Young
Motorola
Larry Smith wrote:
> ... I have compared the results of IBIS simulation to that of
full
> HSPICE model simulation and hardware measurements for several
different
> transmission line problems. IBIS model simulation compares
very well to
> both.