[SI-LIST] : =?ISO-8859-1?Q?[SI-LIST]:_2nd_IEEE_Workshop_=22Signal_Propagation_on_Interconnects=22?=

Treytnar Dieter ([email protected])
Tue, 17 Mar 1998 17:15:38 +0100

2nd IEEE Computer Society



May 13-15, 1998

Kurhaus-Hotel, Travemuende, Germany

Current and up-to-date information about the workshop can be found on the
website http://www.tet.uni-hannover.de/SPI/spi.htm .


As a result ot the success of the 1st Workshop on Signal Propagation on
Interconnects we will continue this meeting with the "2nd International
Workshop on Signal Propagation on Interconnects" to be held in Travemuende=
Baltic Sea Side, which will be sponsored by the IEEE Computer Society. It
is the intent of this workshop to report on recent developments and
approaches in the field of interconnect simulation and measurement on chip=
as well as on boards and packages.

The workshop will be held in English. The committee looks forward to your

The topics of the workshop are:
- Ground Effects
- Substrate Influence on Signal Propagation
- Measurement and Modeling
- Simulation of Interconnects
- Parameter Extraction and Modeling
- Interconnect Design
- Numerical Methods in the Time Domain
- Trends in High-Speed Interconnects


Early Registration 6:00 PM - 8:00 PM
Welcome Reception and Buffet 6:00 PM - 9:00 PM

Registration 8:00 AM - 5:00 PM

Opening Session

09:00 Welcome Address
J.P. Mucha, Univ. Hannover, GERMANY

H. Grabinski, Univ. Hannover, GERMANY

09:30 Coffee Break

Session 1: Ground Effects

10:00 The PEEC-Method and its Application by Calculating Impedances of
Complex Power-Ground-Supply Systems
M. Troescher, A. Englmaier, SimLab Software GmbH, Muenchen,

10:30 Analytical Field Solutions for Ground Bounce Investigation
O. Kosch, G. Scheinert, F.H. Uhlmann, Tech. Univ. of Ilmenau,

11:00 Ground and Power Plane Termination Effects in FDTD Simulations
of High-Speed Via Interconnect Structures
Ch. Schuster 1, S. Iranzo 2, P. Regli 1, W. Fichtner 1, 1ETH
Zuerich, 2CERN, Geneva, SWITZERLAND

11:30 Impact of the Ground Configuration in Deep Submicron Integrated
C. Cregut 1, G. LeCarval 2, J. Chilo1, 1PFT-CEM, St Martin
d'H=E9res, 2LETI, Grenoble, FRANCE

12:30 Lunchbuffet

Session 2: Substrate Influence on Signal Propagation

14:00 Efficient Computation of the Parameters of Parallel Transmission
Lines in IC Interconnects
M. Grimm, H.K. Dirks, Univ. Kiel, GERMANY

14:30 Interconnection Modeling for Coplanar Lines on Silicon
A. Owzar 1, A.H. Mohammadian 2, M.K. Dadkhah 2, 1Deutsche
Telekom AG, Darmstadt, GERMANY, 2Rockwell Science Center,
Thousand Oaks, USA

15:00 The One-Dimensional Metal-Insulator-Semiconductor Transmission
D.F. Williams, NIST, Boulder, USA

15:30 Coffee Break and Postersession

Session 3: Measurement and Modeling

16:30 Accurate Characteristic Impedance Measurement on Silicon
U. Arz1, H. Grabinski 1, D.F. Williams 2, 1Univ. Hannover,
Boulder, USA

17:00 Measurement of Signal Commutation on Deep Sub-micron
F. Caignet 1, S. Delmas1, P. Solignac1, E. Sicard 1, P. Saintot
2, J.G. Ferrante3, 1INSA, Toulouse, 2SGS-Thomson, Grenoble,
3Matra Systeme, Toulouse, FRANCE

17:30 Effect of Material and Interconnect Parameters on Leaded Package
Y. Qiu1, M.K. Iyer 1, K.C. Chong 1, T.C. Wong 2, E. Chong 3,
1Inst. of Microelectronics, 2Siemens Components, 3ESEC (Asia

18:00 Determination of the Substrate Influences on Signal Propagation
on Coupled Lines
on Chips Using High Frequency Measurements
T.-M. Winkel 1, L.S. Dutta 2, 1IBM Deutschland Entwicklungs
GmbH, Boeblingen, 2Siemens HL, Muenchen, GERMANY

Registration 8:00 AM - 4:00 PM

Session 4: Simulation of Interconnects I

08:30 An Error Bound in Interconnect Simulation using PRIMA
E. Chiprout, IBM Austin Res. Lab, USA

09:00 Addressing Passivity Issues in High-Speed Interconnect
R. Achar, M. Nakhla, Carleton Univ., CANADA

09:30 Coffee Break

Session 5: Parameter Extraction and Modeling

10:00 Simplified Model Extraction of 3D Conductors
S. Boehringer, H. Harrer, IBM Deutschland Entwicklungs GmbH,
Boeblingen, GERMANY

10:30 Capacitance Calculation Using a Vertex Based Finite Volume
Technique on Irregular Grids
N. Orhanovic, Mentor Graphics Corp., Wilsonville, USA

11:00 Compact Modeling of Interconnect Lines at GHz Frequencies
R. Lowther, W.R. Hibner, Harris Semiconductor, Melbourne, USA

11:30 Simplified Process Based 3D Interconnect Modeling for Automatic
Capacitance Extraction
D. Meyer 1, M.R. Frerichs1, E. Barke 2, 1Siemens AG, Muenchen,
2Univ. Hannover, GERMANY

12:30 Lunchbuffet

Session 6: Simulation of Interconnects II

14:00 Time-Domain Space Expansion Simulation of Nonuniform High-Speed
Packaging Interconnects
S. Grivet-Talocia, F.G. Canavero, Politecnico di Torino, ITALY

14:30 Transient Analysis of n-Wire Interconnects by Means of
Time-Domain Scattering Parameters
W. Bandurski, Pozna Univ., POLAND

15:00 Modeling of Digital Circuits via NARX Identification
F.G. Canavero, I.S. Stievano, I.A. Maio, Politecnico di Torino,

15:30 Coffee Break and Postersession

Session 7: Interconnect Design

16:30 Bus Pumping at GBit/s Data Rate on MCM
G.A. Katopis, T. Lo, M.F. McAllister, C.K. Vakirtzis, D. Becker,
IBM Corp.,
Poughkeepsie, USA

17:00 Interconnect Effects on Performance of Field Programmable Analog
D. Anderson1, C. Birk 2, O.A. Palusinski 3, M. Spitz 4, K. Reiss
2, 1Motorola, SPS, Phoenix, USA, 2Univ. Karlsruhe, GERMANY,
3Univ. of Arizona, Tucson, USA, 4Tech. Univ. of Pozna, POLAND

17:30 Characterization of Simultaneous Switching Noise on a CMOS Chip
Simulations and Measurements
P. Lin, S. Kuppinger, IBM Corp., Poughkeepsie, USA

19:30 Social Event: =BBWaterkantabend=AB on board of a ship; Buffet


Session 8: Numerical Methods in the Time Domain

08:30 Electromagnetic Simulation of Signal Cross-Talk between
Transmission Lines Shielded by Vias
L. Zhao, J.L. Prince, Univ. of Arizona, Tucson, USA

09:00 Extraction of Equivalent Circuit Parameters of Interconnections
Using FDTD and PML
F. Liu, J.E. Schutt-Ain=E9, Univ. of Illinois, Urbana, USA

09:30 Combination of 1-D FDTD and Lumped Elements in Simulation of
Packaging Interconnects
S.Y. Chang, A.C. Cangellaris, J.L. Prince, Univ. of Arizona,
Tucson, USA

10:00 A Study of Vias and Microvias
R. Abhari, T.E. van Deventer, Univ. of Toronto, CANADA

10:30 Coffee Break

Session 9: Trends in High-Speed Interconnects

11:00 Challenges for Interconnect Simulation in High-Speed Digital
Board and System Design
H. Ibowski, W. Schnell, Siemens AG, Muenchen, GERMANY

11:30 Replacing Electrical by Optical Interconnections within
High-Speed Electronic Systems
E. Griese 1, A. Himmler 2, 1Siemens Nixdorf Informationssysteme
AG / C-LAB, Paderborn, 2Univ.-GH Paderborn / C-LAB, GERMANY

12:00 Discussion and Summary
J.P. Mucha, Univ. Hannover, GERMANY

Workshop Committee

GENERAL CHAIR: J. P. Mucha, Univ. Hannover (D)
VICE CHAIR: T. W. Williams, Synopsys, Mount. View (USA)
PROGRAM CHAIR: H. Grabinski, Univ. Hannover (D)
CO-CHAIR: P. Nordholz, Univ. Hannover (D)

Technical Program Committee

W. Bandurski, Univ. Pozna (PL)
F. Canavero, Univ. Torino (I)
D. De Zutter, Univ. Gent (B)
H.-J. John, Siemens-Nixdorf, Paderborn (D)
E. Kuh, Univ. of California, Berkeley (USA)
N. van der Meijs, Univ. Delft (NL)
J.P. Mucha, Univ. Hannover (D)
P. Nordholz, Univ. Hannover (D)
O.A. Palusinski, Univ. of Arizona, Tucson (USA)
H.J. Pfleiderer, Univ. Ulm (D)
L.T. Pileggi, Carnegie Mellon Univ., Pittsburgh (USA)
H. Reichl, FhG-IZM, Berlin (D)
K. Reiss, Univ. Karlsruhe (D)
A. Rubio, Univ. UPC Barcelona (E)
A.E. Ruehli, IBM Corp., Yorktown Heights (USA)
J. Schutt-Ain=E9, Univ. of Illinois, Urbana (USA)
E. Sicard, INSA, Toulouse (F)
R. Velazco, TIMA, Grenoble (F)
D.F. Williams, NIST, Boulder (USA)
T.W. Williams, Synopsys, Inc., Mountain View (USA)
Y. Zorian, AT&T Bell Labs, Princeton (USA)

Workshop Fees

Registration Registration
before after
April 15 April 15
IEEE Member DM 510 DM 550
Non-member DM 625 DM 700

The registration fee includes: meals, workshop registration package,
refreshments, and social event.
This is an unbreakable package.


Hotel reservations must be made directly with:

Kurhaus-Hotel Travemuende
Reservation IEEE Workshop"
Aussenallee 10
D-23570 Luebeck-Travemuende
Tel.: +49-4502-881-0
Fax: +49-4502-74437

There are special room rates for workshop attendees:

Category 1
Single Room/day: DM 179
Double Room/day: DM 248

Category 2
Single Room/day: DM 159
Double Room/day: DM 228

A full breakfast menu is included in the room rates.

Since the number of rooms is limited in both categories reservations shoul=
be made as soon as possible and can only be accepted on a space available
basis. Please be sure to mention that you are attending the IEEE Workshop.


Travemuende is located 80km north-east of Hamburg at the Baltic Sea Side.
=46rom Hamburg-Fuhlsbuettel airport there is a bus shuttle to Hamburg Cent=
Station every 20 minutes (DM 8) or a taxi (DM 25 to DM 35). There are trai=
connections every hour to Travemuende.

The hotel is located only 200 mtrs. from the railway station in Travemuend=



To register, mail this form (or a copy of this form) with
payment to:

Petra Nordholz
Laboratorium fuer Informationstechnologie
Schneiderberg 32
D-30167 Hannover, GERMANY

Phone: +49-511-762-5032
Fax: +49-511-762-5051
Email: [email protected]

Registrations via fax can be accepted only with credit card
The workshop fee must be paid by credit card, check or cash. For
check-payments from non-German banks you have to pay a collectio=
fee of DM 30 in addition to the workshop fee.

Please type or print clearly:

Name ______________________________________________

Affiliation _________________________________________

Mailing Address ______________________________________


Zip _______ City ___________________________________

Country ________________ Fax _______________________

Phone ______________________________________________

Email ______________________________________________

IEEE Membership No. ___________________________________

For payment by credit card please indicate:

O [Image] O [Image] O [Image]

Card Number _________________________________________

Exp. Date ____________ Amount to be charged DM _________

Signature ________________________ Date _______________


Dipl.-Ing. Dieter Treytnar
Laboratorium fuer Informationstechnologie
Schneiderberg 32 D-30167 Hannover, Germany
Tel. +49-511-762-5056 Fax +49-511-762-5052
E-Mail: [email protected] [email protected] [email protected]=