Re: [SI-LIST] : power supply filtering and bypassing

Ravinder Ajmani ([email protected])
Thu, 5 Mar 1998 17:00:33 -0500

One suggestion I can make is to use a separate power plane for these ch=
Feed this power plane through an inductor that connects to a bulk tanta=
capacitor (15-20 uF) and a 0.1 uF ceramic capacitor. This arrangement =
provide a local reservoir for the power supply that will reduce the eff=
ect of
the power supply variations.
Still better arrangement will be to have a separate linear regulator fo=
r this
power plane.

Regards, Ravinder
PCB Development and Design Department
IBM Corporation - Storage Systems Division
Voice : (408) 256-7956 T/L : 276-7956 Fax : (408) 256-0550=

Email: [email protected]
Always do right. This will gratify some people and astonish the rest. =
Mark Twain

[email protected] on 03/05/98 12:28:51 PM
Please respond to [email protected] @ internet
To: [email protected] @ internet
Subject: [SI-LIST] : power supply filtering and bypassing

I was browsing the web and happen to bump into this discussion group. T=
discussions look to be pretty broad, so I hope by me being specific
doesn't violate the scope of the group.

I've been working with a high-speed (1Ghz+) point-to-point data link
chipset from HP called GLINK (HDMP-1022/HDMP-1024). Both receiver and
transmitter have built-in PLLs used for Transmit Clock generation and
Receive Clock extraction.
The application is PC based so I've been having problems attempting to
use off-the-shelf ATX PC switching power supplies.(i.e. 250W ASTEC) I'v=
discovered that the supplies have horrible (under and over shoot)
transients ([email protected]) causing loss of lock on the receive end.=
guess I shouldn't expect a lot for 30 bucks!!

The noise seems to correlate with disk accesses mostly (but even mouse
movement shows up), so I'm guessing the supplies have a regulation
problem with variable loads. I haven't gone as far as looking spectrall=
at this because I'm not sure what frequencies and DB levels would cause=

resonance and/or phase problems in the GLINK . I'm guessing this noise =
coupling in on the TX PLL causing enough/or right frequency jitter so
the receiver PLL loses track. If I cut the boards VCC line and wire in =
linear supply(don't use the PC's VCC, but use the GND), the link stays
solid. The only supply filtering recommendation from HP is the catch-a=
0.1uf bypass, but this doesn't seem suitable, so I ask the following.

What is the best way to measure the frequency content of the noise?

Any good reference articles or papers for this situation?

I'm planning a layout change, separating the GLINK's power and ground
layer from the rest of the PCB and use a pi filtering arrangement to
connect the planes, I'm not sure what filter values would be acceptable=

or if this is the right approach at all, any ideas?


Kevin Skey
Northstar Technologies
[email protected]
978-897-6600 x168