I've got an issue that I'd like to hear some of your opinions on. How
many of you have had problems letting the reverse biased diode clamp
overshoot and undershoot at the input of a bi-directional LVTTL CMOS?
Specifically have you identified root causes. I'm looking for why, and
not, oh, it flipped a bit. I can easily model at least one effect if I
can get reasonable silicon routed models. That is internal ground/power
bounce on the silicon. I suspect most semiconductor vendors can and do
the same. Another issue might be electromigration which is basically a
quality issue. e.g. it reduces to an energy verses defect rate tradeoff.
If we were to quantify a design that minimized the effects of
aforementioned what else should be identified. I know that some
devices many not have this reverse diode behavior. I am not referring
to devices that do not. Also I do not believe I'm referring to ESD
diodes either. I firmly believe that if I can quantify the nature and
impact of these effect I can make trade off decision on how much I can
tolerate.
I did have a rather strange problem a while back with undershoot on an
output buffer (not input). Excessive undershoot at the driver caused it
to spurious fire out a runt pulse of 1-2 ns. This was on rather old TTL
technology. I thinks this may have been a diode transit timing charging
effect.
Oh, BTW, many, many DIMM's we've measured have more that 1.5v of over
and undershoot for 1-4 ns.
... Rich Mellitz, Intel