Re: [SI-LIST] : Down-bond in chip packaging

Yehuda D. Yizraeli ([email protected])
Tue, 10 Feb 1998 08:41:29 +0200 (EET)


I will agree with your approach if the package has rails, namely
separated power planes for its use, however, i meant a plane-less package
inwhich the cavity is used as the down-bond plane which means noise is injected
to the whole core, doesn't it..?

Regards, yehuda

> Yehuda D. Yizraeli wrote:
> > I am inveswtigating the various options of using the down bonds
> > for our design. naturaly, one would like to connect all the VSS to the
> > down-bond plate. However, the periphery supply, which makes the most
> > noise, can then inject noise into the core logic, especialy to the PLL
> > circuitry through the substrate (influencing input buffers' trip-point
> > as well). So, my conclusion is to conect core and other non periphery
> > VSS to the down-bond plate (paddle) and the periphery should be directly
> > connected to the packages' pins.
> >
> > Do u agree with the analysis, can u point me to some areticles
> > and/or literture on the subject..?
> Our standard practice is just the opposite. Core current is
> generally balanced so onchip bypassing takes care of the worst
> of the high-frequency components, while most I/O types are
> unbalanced and heavily dependent on supply inductance. We
> run the I/O ring VSS and VDD supplies to the package rails
> and supply core through either signal or secondary supply
> balls. Either way, PLL supplies are as completely isolated
> as possible, with no connection to either core or I/O supplies
> short of the PWB planes.
> --
> D. C. Sessions
> [email protected]

   Yehuda D. Yizraeli

Zoran Microelectronics Ltd. E-mail: [email protected] Advanced Technology Center Tel: 972-4-8545795 P.O.B. 2495, Haifa 31204, Israel Fax: 972-4-8551550 -------------------------------------------------------------------