[SI-LIST] : Down-bond in chip packaging

Yehuda D. Yizraeli ([email protected])
Mon, 9 Feb 1998 00:17:45 +0200 (EET)


I am inveswtigating the various options of using the down bonds
for our design. naturaly, one would like to connect all the VSS to the
down-bond plate. However, the periphery supply, which makes the most
noise, can then inject noise into the core logic, especialy to the PLL
circuitry through the substrate (influencing input buffers' trip-point
as well). So, my conclusion is to conect core and other non periphery
VSS to the down-bond plate (paddle) and the periphery should be directly
connected to the packages' pins.

Do u agree with the analysis, can u point me to some areticles
and/or literture on the subject..?

Thanks in advance for the help, yehuda

   Yehuda D. Yizraeli

Zoran Microelectronics Ltd. E-mail: [email protected] Advanced Technology Center Tel: 972-4-8545795 P.O.B. 2495, Haifa 31204, Israel Fax: 972-4-8551550 http://www.zoran.com -------------------------------------------------------------------