We, the design comunity, will be more than pleased with helping-facts,
like whats the difference in the chips between suppliers (good and bad), and other
data which might help us.
thanks in advance, yehuda
>
> Chaps,
> I've been following this ( see bottom of message ) discussion with a lot of
> interest. I have faced an ASIC problem recently ( hope to publish what I've
> found very soon ) which is directly related to the issue of noise on NON
> switching signals.
>
> The subject is low cost controllers, an ASIC was a great way to combine
> discrete devices to recoup board space etc etc from earlier versions. However,
> the ASIC is used not only to control many lines of I/O leaving the controller,
> but signals between the uP, its memory, and an onboard A to D convertor.
> Because all signals use the ASIC, the I/O lines have remnents of the really
> fast switching on them.
>
> I can't afford to filter each line, the whole product DMC is less than $30! I
> have looked at several vendors parts and discovered there is a big difference
> between them from this aspect. Being an EMC guy rather than a Silicon guy I
> don't fully appreciate why. I'm nervous though that if my current good
> supplier goes, my whole controller range will fail EMC tests.
>
> I guess this posting was to make sure that folks designing chips know that the
> EMC chaps are very interested in things like "crosstalk" between lines being
> switched. Even if it's not considdered of primary importance to the SI
> engineer.
>
> Best regards,
>
> Derek N. Walton
> Owner L F Research EMC Design and Test Facility
>
>
>
> In a message dated 98-01-08 10:26:35 EST, [email protected] writes:
>
> << Andrew Ingraham wrote:
> >
> > > One thing that has always concerned me with SSO is the affect of the VCC
> > > drop on non-switching signals. Theses signal would have noise on them
> > > that would mimic the VCC noise on chip (since their outputs are
> > > effectively shorted to VCC).
> >
> > Indeed. Even worse, since noise margin is usually smaller in the
> > low state than the high state, is the GND bounce killing your noise
> > margin on those outputs that are supposed to be LOW.
> >
> > You may need to assume that ALL outputs go indeterminate on every
> > clock cycle, whether they switch or not. Clock or clock-like
> > outputs need special treatment to keep them usable as clocks.
>
> Absolutely. Synchronous systems specifically tolerate noise on
> non-switching signals except during sample windows, which moots
> the noise issue. Clocks, IMNSHO, should be differential signals
> anyway for a whole slew of reasons, this not least.
> >>
>
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