I have been doing a timing analysis for an interface between a processor
and SRAM. During a read/write cycle turnaround I have hit on the
situation where in absolute worst-case conditions there can be a clash
on the data bus.
I have always tried to avoid such a situation having been told that this
causes large transient currents leading to excessive board noise and
reduces the reliability of the I/O drivers and other such fire and
brimstone ...
I am wondering whether anyone has done some closer analysis on this
subject. I presume that the severity of the problem will depend on a
number of things such as:
- how long the clash can potentially last for
- how much loss due to back-matching resistors is provided
- how long the traces are
Any hints on how to determine how bad such a situation would really be?
Thanks,
Andrew Phillips
Supercomputing Systems AG
Zurich, Switzerland